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* add a few more missing dffPepijn de Vos2019-10-211-7/+16
* add negedge DFFPepijn de Vos2019-10-212-15/+139
* use ADDSUB ALU mode to remove invertersPepijn de Vos2019-10-212-7/+77
* remove duplicate DFFRPepijn de Vos2019-10-161-10/+0
* Revert "add MUX support"Pepijn de Vos2019-09-063-17/+0
* fix BRAM width and initPepijn de Vos2019-09-062-12/+28
* add more DFF to sim libPepijn de Vos2019-09-062-6/+111
* WIP aditional DFF primitivesPepijn de Vos2019-09-052-1/+48
* support bram initialisationPepijn de Vos2019-09-055-3/+25
* use singleton ground and vcc nets, apparently this makes pnr happierPepijn de Vos2019-09-051-1/+1
* add MUX supportPepijn de Vos2019-09-053-0/+17
* set undriven pads to zeroPepijn de Vos2019-09-041-0/+1
* Merge remote-tracking branch 'diego/gowin'Pepijn de Vos2019-09-042-2/+2
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| * Updating gowinDiego H2019-09-022-2/+2
* | gowin: add splitnets to appease the PnRPepijn de Vos2019-09-041-0/+1
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* Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-011-2/+2
* Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-masterClifford Wolf2019-04-2210-10/+458
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| * GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flowDiego2019-04-1210-11/+459
* | Make nobram false by default for gowinMiodrag Milanovic2019-04-021-1/+1
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* Reduce amount of trailing whitespace in code baseLarry Doolittle2019-02-282-7/+7
* Unify usage of noflatten among architecturesMiodrag Milanovic2019-01-041-3/+11
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
* Changes in GoWin synth commands and ALU primitive supportDiego H2018-12-034-4/+83
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-4/+4
* Indenting fixes in gowin sim cell libClifford Wolf2016-11-081-20/+28
* Added hex constant support to write_verilogClifford Wolf2016-11-031-1/+1
* Added initial version of "synth_gowin"Clifford Wolf2016-11-014-0/+266
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