| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Indenting fixes in gowin sim cell lib | Clifford Wolf | 2016-11-08 | 1 | -20/+28 |
| * | Added hex constant support to write_verilog | Clifford Wolf | 2016-11-03 | 1 | -1/+1 |
| * | Added initial version of "synth_gowin" | Clifford Wolf | 2016-11-01 | 4 | -0/+266 |
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index : iCE40/yosys | |
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