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* add -noalu and -json option for apiculaPepijn de Vos2020-11-301-3/+32
* synth_gowin: Add rPLL blackboxKonrad Beckmann2020-11-111-0/+45
* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-071-4/+4
* gowin: Use dfflegalize.Marcelina Kościelnicka2020-07-062-145/+41
* synth_gowin: ABC9 supportDan Ravensloft2020-07-052-34/+340
* Merge pull request #2232 from YosysHQ/mwk/gowin-sim-initMarcelina Kościelnicka2020-07-051-8/+8
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| * gowin: Fix INIT values in sim library.Marcelina Kościelnicka2020-07-051-8/+8
* | gowin: replace determine_init with setundefDan Ravensloft2020-07-043-74/+1
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* Update dff2dffe, dff2dffs, zinit to new FF types.Marcelina Kościelnicka2020-06-232-25/+25
* Use C++11 final/override keywords.whitequark2020-06-182-6/+6
* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-192-0/+9
* gowin,ecp5: remove generated files in `make clean`.whitequark2020-04-241-2/+1
* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-1/+0
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-5/+5
* Removing cells_sim.v from bram techmap passDiego H2020-02-061-1/+1
* synth_*: call 'opt -fast' after 'techmap'Eddie Hung2020-02-051-1/+1
* Add opt_lut_ins pass. (#1673)Marcelina Kościelnicka2020-02-031-0/+1
* Merge pull request #1604 from whitequark/unify-ram-namingwhitequark2020-01-025-15/+18
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| * Harmonize BRAM/LUTRAM descriptions across all of Yosys.whitequark2020-01-015-15/+18
* | Disable synth_gowin -abc9 as it offers no advantages yetEddie Hung2019-12-301-12/+12
* | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-301-1/+1
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* Use -match-init to not synth contradicting init valuesPepijn de Vos2019-12-031-1/+1
* attempt to fix formattingPepijn de Vos2019-11-251-154/+154
* gowin: add and test dff init valuesPepijn de Vos2019-11-252-41/+199
* gowin: Add missing .gitignore entriesMarcin Kościelnicki2019-11-221-0/+2
* Remove dff init altogetherPepijn de Vos2019-11-192-3/+3
* add help for nowidelut and abc9 optionsPepijn de Vos2019-11-181-1/+7
* fix fsm test with proper clock enable polarityPepijn de Vos2019-11-111-4/+4
* fix wide lutsPepijn de Vos2019-11-061-12/+12
* add IOBUFPepijn de Vos2019-10-282-1/+10
* add tristate buffer and testPepijn de Vos2019-10-282-2/+8
* More formattingPepijn de Vos2019-10-281-55/+49
* really really fix formatting maybePepijn de Vos2019-10-281-41/+41
* undo formatting fuckupPepijn de Vos2019-10-281-25/+25
* add wide lutsPepijn de Vos2019-10-283-36/+119
* add 32-bit BRAM and byte-enablesPepijn de Vos2019-10-282-4/+25
* ALU sim tweaksPepijn de Vos2019-10-241-11/+11
* add a few more missing dffPepijn de Vos2019-10-211-7/+16
* add negedge DFFPepijn de Vos2019-10-212-15/+139
* use ADDSUB ALU mode to remove invertersPepijn de Vos2019-10-212-7/+77
* remove duplicate DFFRPepijn de Vos2019-10-161-10/+0
* Revert "add MUX support"Pepijn de Vos2019-09-063-17/+0
* fix BRAM width and initPepijn de Vos2019-09-062-12/+28
* add more DFF to sim libPepijn de Vos2019-09-062-6/+111
* WIP aditional DFF primitivesPepijn de Vos2019-09-052-1/+48
* support bram initialisationPepijn de Vos2019-09-055-3/+25
* use singleton ground and vcc nets, apparently this makes pnr happierPepijn de Vos2019-09-051-1/+1
* add MUX supportPepijn de Vos2019-09-053-0/+17
* set undriven pads to zeroPepijn de Vos2019-09-041-0/+1
* Merge remote-tracking branch 'diego/gowin'Pepijn de Vos2019-09-042-2/+2
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