index
:
iCE40/yosys
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
techlibs
/
gowin
/
synth_gowin.cc
Commit message (
Expand
)
Author
Age
Files
Lines
*
fix BRAM width and init
Pepijn de Vos
2019-09-06
1
-1
/
+1
*
support bram initialisation
Pepijn de Vos
2019-09-05
1
-1
/
+1
*
use singleton ground and vcc nets, apparently this makes pnr happier
Pepijn de Vos
2019-09-05
1
-1
/
+1
*
add MUX support
Pepijn de Vos
2019-09-05
1
-0
/
+1
*
set undriven pads to zero
Pepijn de Vos
2019-09-04
1
-0
/
+1
*
Merge remote-tracking branch 'diego/gowin'
Pepijn de Vos
2019-09-04
1
-1
/
+1
|
\
|
*
Updating gowin
Diego H
2019-09-02
1
-1
/
+1
*
|
gowin: add splitnets to appease the PnR
Pepijn de Vos
2019-09-04
1
-0
/
+1
|
/
*
Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master
Clifford Wolf
2019-04-22
1
-9
/
+45
|
\
|
*
GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow
Diego
2019-04-12
1
-10
/
+46
*
|
Make nobram false by default for gowin
Miodrag Milanovic
2019-04-02
1
-1
/
+1
|
/
*
Reduce amount of trailing whitespace in code base
Larry Doolittle
2019-02-28
1
-1
/
+1
*
Unify usage of noflatten among architectures
Miodrag Milanovic
2019-01-04
1
-3
/
+11
*
Fix typographical and grammatical errors and inconsistencies.
whitequark
2019-01-02
1
-1
/
+1
*
Changes in GoWin synth commands and ALU primitive support
Diego H
2018-12-03
1
-4
/
+17
*
Consistent use of 'override' for virtual methods in derived classes.
Henner Zeller
2018-07-20
1
-4
/
+4
*
Added hex constant support to write_verilog
Clifford Wolf
2016-11-03
1
-1
/
+1
*
Added initial version of "synth_gowin"
Clifford Wolf
2016-11-01
1
-0
/
+178