| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | better handling of lut and begin/end add | Miodrag Milanovic | 2019-09-18 | 1 | -4/+10 |
| * | Added simulation models for Efinix and Anlogic | Miodrag Milanovic | 2019-09-15 | 1 | -2/+62 |
| * | Fix missing newline at end of file | Clifford Wolf | 2019-08-22 | 1 | -1/+1 |
| * | Fix formating | Miodrag Milanovic | 2019-08-11 | 1 | -2/+2 |
| * | one bit enable signal | Miodrag Milanovic | 2019-08-11 | 1 | -1/+1 |
| * | fix mixing signals on FF mapping | Miodrag Milanovic | 2019-08-11 | 1 | -4/+4 |
| * | Replaced custom step with setundef | Miodrag Milanovic | 2019-08-11 | 3 | -91/+1 |
| * | Fixed data width | Miodrag Milanovic | 2019-08-11 | 1 | -2/+2 |
| * | Adding new pass to fix carry chain | Miodrag Milanovic | 2019-08-11 | 3 | -0/+124 |
| * | cleanup | Miodrag Milanovic | 2019-08-11 | 1 | -4/+7 |
| * | Fix CO | Miodrag Milanovic | 2019-08-09 | 1 | -26/+24 |
| * | clock for ram trough gbuf | Miodrag Milanovic | 2019-08-04 | 1 | -0/+6 |
| * | Added bram support | Miodrag Milanovic | 2019-08-04 | 6 | -1/+260 |
| * | Custom step to add global clock buffers | Miodrag Milanovic | 2019-08-03 | 4 | -1/+129 |
| * | Initial EFINIX support | Miodrag Milanovic | 2019-08-03 | 5 | -0/+370 |
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index : iCE40/yosys | |
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