| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth_*: call 'opt -fast' after 'techmap' | Eddie Hung | 2020-02-05 | 1 | -0/+1 |
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| * | Merge pull request #1604 from whitequark/unify-ram-naming | whitequark | 2020-01-02 | 3 | -6/+18 |
| |\ | | | | | Harmonize BRAM/LUTRAM descriptions across all of Yosys | ||||
| | * | Harmonize BRAM/LUTRAM descriptions across all of Yosys. | whitequark | 2020-01-01 | 3 | -6/+18 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit: * renames all remaining instances of "DRAM" (which is ambiguous) to "LUTRAM" (which is not), finishing the work started in the commit 698ab9be; * renames memory rule files to brams.txt/lutrams.txt; * adds/renames script labels map_bram/map_lutram; * extracts where necessary script labels map_ffram and map_gates; * adds where necessary options -nobram/-nolutram. The end result is that BRAM/LUTRAM/FFRAM aspects of every target are now consistent with each other. Per architecture: * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add :map_lutram, :map_ffram, :map_gates * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram, :map_gates * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt, rename -nodram→-nolutram (-nodram still recognized), rename :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates | ||||
| * | | Update doc that "-retime" calls abc with "-dff -D 1" | Eddie Hung | 2019-12-30 | 1 | -2/+2 |
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| * | FF should be initialized to 0 | Miodrag Milanovic | 2019-10-04 | 1 | -1/+3 |
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| * | Add missing latch mapping | Miodrag Milanovic | 2019-10-04 | 1 | -0/+12 |
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| * | better handling of lut and begin/end add | Miodrag Milanovic | 2019-09-18 | 1 | -4/+10 |
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| * | Added simulation models for Efinix and Anlogic | Miodrag Milanovic | 2019-09-15 | 1 | -2/+62 |
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| * | Fix missing newline at end of file | Clifford Wolf | 2019-08-22 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Fix formating | Miodrag Milanovic | 2019-08-11 | 1 | -2/+2 |
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| * | one bit enable signal | Miodrag Milanovic | 2019-08-11 | 1 | -1/+1 |
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| * | fix mixing signals on FF mapping | Miodrag Milanovic | 2019-08-11 | 1 | -4/+4 |
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| * | Replaced custom step with setundef | Miodrag Milanovic | 2019-08-11 | 3 | -91/+1 |
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| * | Fixed data width | Miodrag Milanovic | 2019-08-11 | 1 | -2/+2 |
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| * | Adding new pass to fix carry chain | Miodrag Milanovic | 2019-08-11 | 3 | -0/+124 |
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| * | cleanup | Miodrag Milanovic | 2019-08-11 | 1 | -4/+7 |
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| * | Fix CO | Miodrag Milanovic | 2019-08-09 | 1 | -26/+24 |
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| * | clock for ram trough gbuf | Miodrag Milanovic | 2019-08-04 | 1 | -0/+6 |
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| * | Added bram support | Miodrag Milanovic | 2019-08-04 | 6 | -1/+260 |
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| * | Custom step to add global clock buffers | Miodrag Milanovic | 2019-08-03 | 4 | -1/+129 |
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| * | Initial EFINIX support | Miodrag Milanovic | 2019-08-03 | 5 | -0/+370 |
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index : iCE40/yosys | |
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