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* ecp5: latches_map.v if *not* -asyncprldEddie Hung2020-05-141-2/+2
* ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.vEddie Hung2020-05-144-43/+3
* ecp5: fix rebase mistakeEddie Hung2020-05-141-3/+3
* ecp5: TRELLIS_FF bypass path only in async modeEddie Hung2020-05-141-8/+8
* xilinx/ice40/ecp5: zinit requires selected wires, so select them allEddie Hung2020-05-141-1/+1
* xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cellsEddie Hung2020-05-141-3/+26
* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-141-1/+1
* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-141-1/+1
* Revert "ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init"Eddie Hung2020-05-143-220/+64
* ecp5: (* abc9_flop *) gated behind YOSYSEddie Hung2020-05-141-0/+2
* ecp5: add synth_ecp5 -dff to work with -abc9Eddie Hung2020-05-142-12/+47
* ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-initEddie Hung2020-05-143-64/+220
* ecp5: Add missing SERDES parametersDavid Shah2020-05-121-0/+4
* synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpadEddie Hung2020-05-041-0/+13
* gowin,ecp5: remove generated files in `make clean`.whitequark2020-04-241-0/+9
* ecp5: ecp5_gsr to skip cells that don't have GSR parameter againEddie Hung2020-04-221-1/+1
* Cleanup use of hard-coded default parameters in light of #1945Eddie Hung2020-04-222-12/+6
* ecp5: Force SIGNED ports to be 1 bitDavid Shah2020-04-161-1/+1
* Get rid of dffsr2dff.Marcelina Koƛcielnicka2020-04-151-1/+0
* Merge pull request #1603 from whitequark/ice40-ram_stylewhitequark2020-04-103-1/+74
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| * ecp5: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-1/+3
| * ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-062-0/+71
* | kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-022-24/+24
* | Merge pull request #1716 from zeldin/ecp5_fixN. Engelhardt2020-03-091-2/+0
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| * | remove unused parametersN. Engelhardt2020-03-061-3/+0
| * | ecp5: Add missing parameter to \$__ECP5_PDPW16KDMarcus Comstedt2020-02-221-0/+1
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* | synth_ecp5: use +/abc9_model.vEddie Hung2020-02-271-1/+1
* | ecp5: remove small LUT entriesEddie Hung2020-02-271-24/+6
* | ecp5: deprecate abc9_{arrival,required} and *.{lut,box}Eddie Hung2020-02-277-86/+120
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* synth_*: call 'opt -fast' after 'techmap'Eddie Hung2020-02-051-0/+1
* Add opt_lut_ins pass. (#1673)Marcelina Koƛcielnicka2020-02-031-0/+1
* xilinx/ice40/ecp5: undo permuting LUT masks in lut_mapEddie Hung2020-01-271-77/+55
* Merge remote-tracking branch 'origin/master' into eddie/abc9_mfsEddie Hung2020-01-074-35/+31
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| * Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-064-4/+4
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| * \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-021-2/+2
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| * | | Missing characterEddie Hung2019-12-311-1/+1
| * | | Cleanup ecp5 boxesEddie Hung2019-12-314-35/+31
* | | | Re-enable &mfs for synth_{ecp5,xilinx}Eddie Hung2020-01-061-2/+2
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* | | Merge pull request #1604 from whitequark/unify-ram-namingwhitequark2020-01-024-4/+4
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| * | Harmonize BRAM/LUTRAM descriptions across all of Yosys.whitequark2020-01-014-4/+4
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* | Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-301-1/+1
* | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-301-1/+1
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* Nitpick cleanup for ecp5Eddie Hung2019-12-272-11/+3
* Revert "Optimise write_xaiger"Eddie Hung2019-12-201-5/+0
* Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanupEddie Hung2019-12-191-0/+5
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| * techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaigerEddie Hung2019-12-061-0/+5
* | Merge pull request #1563 from YosysHQ/dave/async-prldDavid Shah2019-12-182-4/+28
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| * | ecp5: Add support for mapping PRLD FFsDavid Shah2019-12-072-4/+28
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* / Fix bitwidth mismatch; suppresses iverilog warningEddie Hung2019-12-111-4/+4
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* ecp5: Use new autoname pass for better cell/net namesDavid Shah2019-11-151-0/+1