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* ecp5: Add 'fake' DCU parametersDavid Shah2018-11-091-0/+11
* ecp5: Add blackboxes for ancillary DCU cellsDavid Shah2018-11-091-0/+18
* ecp5: Adding some blackbox cellsDavid Shah2018-11-072-1/+391
* ecp5: Remove DSP parameters that don't workDavid Shah2018-10-221-21/+0
* ecp5: Add DSP blackboxesDavid Shah2018-10-213-1/+118
* ecp5: Sim model fixesDavid Shah2018-10-191-3/+5
* ecp5: Add latch inferenceDavid Shah2018-10-193-3/+12
* ecp5: Disable LSR inversionDavid Shah2018-10-162-21/+21
* BRAM improvementsDavid Shah2018-10-121-11/+16
* ecp5: Adding BRAM maps for all size optionsDavid Shah2018-10-101-1/+64
* ecp5: First BRAM type maps successfullyDavid Shah2018-10-108-10/+76
* ecp5: Script for BRAM IO connectionsDavid Shah2018-10-104-64/+115
* ecp5: Adding BRAM initialisation and configDavid Shah2018-10-095-0/+73
* ecp5: Add blackbox for DP16KDDavid Shah2018-10-051-0/+93
* ecp5: Don't map ROMs to DRAMDavid Shah2018-10-011-0/+1
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-4/+4
* ecp5: Fixing miscellaneous sim model issuesDavid Shah2018-07-161-2/+2
* ecp5: Fixing 'X' issues with LUT simulation modelsDavid Shah2018-07-161-6/+19
* ecp5: ECP5 synthesis fixesDavid Shah2018-07-163-15/+32
* ecp5: Adding synchronous set/reset supportDavid Shah2018-07-142-21/+42
* ecp5: Add DRAM match ruleDavid Shah2018-07-131-0/+4
* ecp5: Cells and mappings fixesDavid Shah2018-07-132-5/+5
* ecp5: Fixing arith_mapDavid Shah2018-07-131-4/+5
* ecp5: Initial arith_map implementationDavid Shah2018-07-133-6/+80
* ecp5: Adding basic synth_ecp5 based on synth_ice40David Shah2018-07-133-7/+345
* ecp5: Adding DFF mapsDavid Shah2018-07-132-1/+30
* ecp5: Adding DRAM mapDavid Shah2018-07-133-1/+76
* ecp5: Adding basic cells_sim and mapper for LUTs up to LUT7David Shah2018-07-132-0/+473
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