iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Add bitwise `$bweqx` and `$bwmux` cells	Jannis Harder	2022-11-30	2	-1/+38
*	simlib: Use optional SIMLIB_GLOBAL_CLOCK to define a global clock signal	Jannis Harder	2022-11-30	1	-2/+8
*	simlib: Silence iverilog warning for `$lut`	Jannis Harder	2022-11-30	1	-1/+1
*	simlib: Fix wide $bmux and avoid iverilog warnings	Jannis Harder	2022-11-30	1	-2/+2
*	satgen, simlib: Consistent x-propagation for `$pmux` cells	Jannis Harder	2022-11-30	1	-4/+11
*	simlib: Simplify recently changed $mux model	Jannis Harder	2022-10-28	1	-4/+2
*	Merge pull request #3526 from jix/mux-simlib-eval	Jannis Harder	2022-10-24	1	-4/+1
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\| *	Consistent $mux undef handling	Jannis Harder	2022-10-24	1	-4/+1
* \|	Add smtmap.v describing the smt2 backend's behavior for undef bits	Jannis Harder	2022-10-20	2	-0/+29
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*	Add the $anyinit cell and the formalff pass	Jannis Harder	2022-08-16	1	-0/+17
*	Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}.	Marcelina Kościelnicka	2022-06-02	1	-0/+9
*	Add $bmux and $demux cells.	Marcelina Kościelnicka	2022-01-28	2	-24/+87
*	Hook up $aldff support in various passes.	Marcelina Kościelnicka	2021-10-02	1	-1/+1
*	Add $aldff and $aldffe: flip-flops with async load.	Marcelina Kościelnicka	2021-10-02	3	-0/+382
*	Add v2 memory cells.	Marcelina Kościelnicka	2021-08-11	1	-0/+169
*	memory: Introduce $meminit_v2 cell, with EN input.	Marcelina Kościelnicka	2021-07-28	1	-0/+24
*	Fix files with CRLF line endings	Claire Xenia Wolf	2021-06-09	1	-318/+318
*	Fixing old e-mail addresses and deadnames	Claire Xenia Wolf	2021-06-08	6	-7/+7
*	abc9: fix SCC issues (#2694)	Eddie Hung	2021-03-29	2	-0/+9
*	memory_dff: Remove now-useless write port handling.	Marcelina Kościelnicka	2021-03-08	1	-6/+7
*	Fix syntax error in adff2dff.v	Marcelina Kościelnicka	2021-02-24	1	-1/+1
*	verilog: significant block scoping improvements	Zachary Snow	2021-01-31	3	-46/+45
*	Fix some trivial typos.	Tom Verbeure	2021-01-03	1	-5/+5
*	Merge pull request #2347 from YosysHQ/mwk/techmap-shift-fixes	clairexen	2020-08-20	1	-67/+35
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\| *	techmap/shift_shiftx: Remove the "shiftx2mux" special path.	Marcelina Kościelnicka	2020-08-20	1	-67/+35
* \|	Merge pull request #2319 from YosysHQ/mwk/techmap-celltype-pattern	clairexen	2020-08-20	1	-1/+1
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\| *	techmap: Add support for [] wildcards in techmap_celltype.	Marcelina Kościelnicka	2020-08-02	1	-1/+1
* \|	Respect \A_SIGNED for $shift	Xiretza	2020-08-18	2	-6/+16
* \|	Replace opt_rmdff with opt_dff.	Marcelina Kościelnicka	2020-08-07	1	-3/+3
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*	simcells: Fix reset polarity for $_DLATCH_???_ cells.	Marcelina Kościelnicka	2020-06-30	2	-5/+5
*	Add new FF types to simplemap.	Marcelina Kościelnicka	2020-06-23	1	-1/+1
*	Add new builtin FF types	Marcelina Kościelnicka	2020-06-23	3	-0/+2293
*	Use C++11 final/override keywords.	whitequark	2020-06-18	2	-8/+8
*	Do not optimize away FFs in "prep" and Verific fron-end	Claire Wolf	2020-06-09	1	-2/+2
*	Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve	Eddie Hung	2020-06-04	1	-1/+1
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\| *	abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_	Eddie Hung	2020-05-29	1	-1/+1
* \|	Add flooring division operator	Xiretza	2020-05-28	2	-0/+71
* \|	Add flooring modulo operator	Xiretza	2020-05-28	2	-3/+124
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*	Add force_downto and force_upto wire attributes.	Marcelina Kościelnicka	2020-05-19	6	-23/+88
*	abc9: use (* abc9_keep ) instead of ( abc9_scc *); apply to $_DFF_?_	Eddie Hung	2020-05-14	2	-14/+2
*	abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it	Eddie Hung	2020-05-14	2	-5/+4
*	abc9_ops/xaiger: further reducing Module::derive() calls by ...	Eddie Hung	2020-05-14	2	-7/+5
*	Cleanup; reduce Module::derive() calls	Eddie Hung	2020-05-14	2	-4/+4
*	abc9: only do +/abc9_map if `DFF	Eddie Hung	2020-05-14	1	-0/+2
*	abc9: not enough to techmap_fail on (* init=1 *), hide them using $__	Eddie Hung	2020-05-14	2	-10/+26
*	abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too	Eddie Hung	2020-05-14	4	-0/+55
*	abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxes	Eddie Hung	2020-05-14	1	-3/+0
*	techlibs/common: more robustness when *_WIDTH = 0	Eddie Hung	2020-05-05	2	-7/+30
*	Fix the truth table for $_SR_* cells.	Marcelina Kościelnicka	2020-04-15	3	-26/+21
*	Merge pull request #1648 from YosysHQ/eddie/cmp2lcu	Eddie Hung	2020-04-03	4	-11/+120
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