iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Install simlib in datdir	Clifford Wolf	2013-11-19	1	-0/+6
*	Cleanups and bugfixes in response to new internal cell checker	Clifford Wolf	2013-11-11	2	-47/+43
*	Fixed techmap of $reduce_xnor with multi-bit outputs	Clifford Wolf	2013-11-07	1	-1/+7
*	Fixed techmap of $gt and $ge with multi-bit outputs	Clifford Wolf	2013-11-06	1	-2/+14
*	Improved width extension with regard to undef propagation	Clifford Wolf	2013-11-06	1	-11/+11
*	Bugfix in dffsr techmap rules	Clifford Wolf	2013-10-18	1	-8/+8
*	Added techmap rules for $sr, $dffsr and $dlatch	Clifford Wolf	2013-10-18	1	-0/+181
*	Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_	Clifford Wolf	2013-10-18	1	-0/+166
*	Added $sr, $dffsr and $dlatch cell types	Clifford Wolf	2013-10-18	1	-20/+76
*	Moved common techlib files to techlibs/common	Clifford Wolf	2013-09-15	5	-0/+2643