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* Add bitwise `$bweqx` and `$bwmux` cellsJannis Harder2022-11-301-0/+37
| | | | | | The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`) cells enable compact encoding and decoding of 3-valued logic signals using multiple 2-valued signals.
* simlib: Use optional SIMLIB_GLOBAL_CLOCK to define a global clock signalJannis Harder2022-11-301-2/+8
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* simlib: Silence iverilog warning for `$lut`Jannis Harder2022-11-301-1/+1
| | | | | | iverilog complains about implicitly truncating LUT when connecting it to the `$bmux` A input. This explicitly truncates it to avoid that warning without changing the behaviour otherwise.
* simlib: Fix wide $bmux and avoid iverilog warningsJannis Harder2022-11-301-2/+2
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* satgen, simlib: Consistent x-propagation for `$pmux` cellsJannis Harder2022-11-301-4/+11
| | | | | This updates satgen and simlib to use a `$pmux` model where the output is fully X when the S input is not all zero or one-hot with no x bits.
* simlib: Simplify recently changed $mux modelJannis Harder2022-10-281-4/+2
| | | | | | The use of a procedural continuous assignment introduced in #3526 was unintended and is completely unnecessary for the actual change of that PR.
* Consistent $mux undef handlingJannis Harder2022-10-241-4/+1
| | | | | | | | | | | | | | | | | | | * Change simlib's $mux cell to use the ternary operator as $_MUX_ already does * Stop opt_expr -keepdc from changing S=x to S=0 * Change const eval of $mux and $pmux to match the updated simlib (fixes sim) * The sat behavior of $mux already matches the updated simlib The verilog frontend uses $mux for the ternary operators and this changes all interpreations of the $mux cell (that I found) to match the verilog simulation behavior for the ternary operator. For 'if' and 'case' expressions the frontend may also use $mux but uses $eqx if the verilog simulation behavior is requested with the '-ifx' option. For $pmux there is a remaining mismatch between the sat behavior and the simlib behavior. Resolving this requires more discussion, as the $pmux cell does not directly correspond to a specific verilog construct.
* Add the $anyinit cell and the formalff passJannis Harder2022-08-161-0/+17
| | | | | | | These can be used to protect undefined flip-flop initialization values from optimizations that are not sound for formal verification and can help mapping all solver-provided values in witness traces for flows that use different backends simultaneously.
* Add $bmux and $demux cells.Marcelina Kościelnicka2022-01-281-23/+49
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* Add $aldff and $aldffe: flip-flops with async load.Marcelina Kościelnicka2021-10-021-0/+49
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* Add v2 memory cells.Marcelina Kościelnicka2021-08-111-0/+169
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* memory: Introduce $meminit_v2 cell, with EN input.Marcelina Kościelnicka2021-07-281-0/+24
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* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* Fix some trivial typos.Tom Verbeure2021-01-031-5/+5
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* Respect \A_SIGNED for $shiftXiretza2020-08-181-4/+12
| | | | | | This reflects the behaviour of $shr/$shl, which sign-extend their A operands to the size of their output, then do a logical shift (shift in 0-bits).
* Add new builtin FF typesMarcelina Kościelnicka2020-06-231-0/+156
| | | | | | | | | | | | | | The new types include: - FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`) - FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`) - FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`) - FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`) - FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`) - latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`) The new FF types are not actually used anywhere yet (this is left for future commits).
* Add flooring division operatorXiretza2020-05-281-0/+43
| | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
* Add flooring modulo operatorXiretza2020-05-281-0/+48
| | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
* Fix the truth table for $_SR_* cells.Marcelina Kościelnicka2020-04-151-1/+1
| | | | | | | | This brings the documented behavior for these cells in line with $_DFFSR_* and $_DLATCHSR_*, which is that R has priority over S. The models were already reflecting that behavior. Also get rid of sim-synth mismatch in the models while we're at it.
* Reformat so it shows up/looks nice when "help $alu" and "help $alu+"Eddie Hung2019-08-091-25/+34
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* A bit more on where $lcu comes fromEddie Hung2019-08-091-0/+2
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* Add more commentsEddie Hung2019-08-091-4/+18
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* Add a few comments to document $alu and $lcuEddie Hung2019-08-081-9/+12
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* Improve $specrule interfaceClifford Wolf2019-04-231-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve $specrule interfaceClifford Wolf2019-04-231-3/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-231-0/+28
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵Clifford Wolf2019-04-231-70/+70
| | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add $specify2 and $specify3 cells to simlibClifford Wolf2019-04-231-0/+147
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add $allconst and $allseq cell typesClifford Wolf2018-02-231-0/+24
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add $live and $fair cell types, add support for s_eventually keywordClifford Wolf2017-02-251-0/+16
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* Add $cover cell type and SVA cover() supportClifford Wolf2017-02-041-0/+8
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* Added $anyseq cell typeClifford Wolf2016-10-141-0/+12
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* Added $global_clock verilog syntax support for creating $ff cellsClifford Wolf2016-10-141-2/+6
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* Added $ff and $_FF_ cell typesClifford Wolf2016-10-121-0/+13
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* Removed $aconst cell typeClifford Wolf2016-08-301-12/+0
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* Removed $predict againClifford Wolf2016-08-281-8/+0
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* Added $anyconst and $aconstClifford Wolf2016-07-271-0/+24
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* Added $initstate cell type and vlog functionClifford Wolf2016-07-211-0/+17
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* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-211-9/+1
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* Added basic support for $expect cellsClifford Wolf2016-07-131-0/+16
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* Improved support for $sop cellsClifford Wolf2016-06-171-3/+3
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* Added $sop cell type and "abc -sop"Clifford Wolf2016-06-171-0/+28
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* Added more cell help messagesClifford Wolf2016-03-291-0/+73
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* Added read-enable to memory modelClifford Wolf2015-09-251-4/+5
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* Added $tribuf and $_TBUF_ sim modelsClifford Wolf2015-08-161-0/+14
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* Another block of spelling fixesLarry Doolittle2015-08-141-2/+2
| | | | Smaller this time
* Added WORDS parameter to $meminitClifford Wolf2015-07-311-1/+2
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* Fixed trailing whitespacesClifford Wolf2015-07-021-2/+2
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* make all vector-size related integer params in $mem sim model signedClifford Wolf2015-04-051-6/+6
| | | | | | this fixes iverilog crashes such as the following: warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647 draw_net_input.c:711: Error: malloc() ran out of memory.
* Added $assume cell typeClifford Wolf2015-02-261-1/+18
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