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authorJannis Harder <me@jix.one>2022-11-02 17:12:51 +0100
committerJannis Harder <me@jix.one>2022-11-30 18:24:35 +0100
commit7203ba7bc1d83777bd2c2c347d45209d8e3d4b84 (patch)
treeda57415b2168bf02cb0efa485a91769850e66cf8 /techlibs/common/simlib.v
parentf2c531e65f4518abe58d04e53d0116583651ac50 (diff)
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Add bitwise `$bweqx` and `$bwmux` cells
The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`) cells enable compact encoding and decoding of 3-valued logic signals using multiple 2-valued signals.
Diffstat (limited to 'techlibs/common/simlib.v')
-rw-r--r--techlibs/common/simlib.v37
1 files changed, 37 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index a22a3fd04..9cb68e725 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1601,6 +1601,43 @@ endmodule
// --------------------------------------------------------
+module \$bweqx (A, B, Y);
+
+parameter WIDTH = 0;
+
+input [WIDTH-1:0] A, B;
+output [WIDTH-1:0] Y;
+
+genvar i;
+generate
+ for (i = 0; i < WIDTH; i = i + 1) begin:slices
+ assign Y[i] = A[i] === B[i];
+ end
+endgenerate
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$bwmux (A, B, S, Y);
+
+parameter WIDTH = 0;
+
+input [WIDTH-1:0] A, B;
+input [WIDTH-1:0] S;
+output [WIDTH-1:0] Y;
+
+genvar i;
+generate
+ for (i = 0; i < WIDTH; i = i + 1) begin:slices
+ assign Y[i] = S[i] ? B[i] : A[i];
+ end
+endgenerate
+
+endmodule
+
+// --------------------------------------------------------
+
module \$assert (A, EN);
input A, EN;