iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Add bitwise `$bweqx` and `$bwmux` cells	Jannis Harder	2022-11-30	1	-0/+37
*	simlib: Use optional SIMLIB_GLOBAL_CLOCK to define a global clock signal	Jannis Harder	2022-11-30	1	-2/+8
*	simlib: Silence iverilog warning for `$lut`	Jannis Harder	2022-11-30	1	-1/+1
*	simlib: Fix wide $bmux and avoid iverilog warnings	Jannis Harder	2022-11-30	1	-2/+2
*	satgen, simlib: Consistent x-propagation for `$pmux` cells	Jannis Harder	2022-11-30	1	-4/+11
*	simlib: Simplify recently changed $mux model	Jannis Harder	2022-10-28	1	-4/+2
*	Consistent $mux undef handling	Jannis Harder	2022-10-24	1	-4/+1
*	Add the $anyinit cell and the formalff pass	Jannis Harder	2022-08-16	1	-0/+17
*	Add $bmux and $demux cells.	Marcelina Kościelnicka	2022-01-28	1	-23/+49
*	Add $aldff and $aldffe: flip-flops with async load.	Marcelina Kościelnicka	2021-10-02	1	-0/+49
*	Add v2 memory cells.	Marcelina Kościelnicka	2021-08-11	1	-0/+169
*	memory: Introduce $meminit_v2 cell, with EN input.	Marcelina Kościelnicka	2021-07-28	1	-0/+24
*	Fixing old e-mail addresses and deadnames	Claire Xenia Wolf	2021-06-08	1	-1/+1
*	Fix some trivial typos.	Tom Verbeure	2021-01-03	1	-5/+5
*	Respect \A_SIGNED for $shift	Xiretza	2020-08-18	1	-4/+12
*	Add new builtin FF types	Marcelina Kościelnicka	2020-06-23	1	-0/+156
*	Add flooring division operator	Xiretza	2020-05-28	1	-0/+43
*	Add flooring modulo operator	Xiretza	2020-05-28	1	-0/+48
*	Fix the truth table for $_SR_* cells.	Marcelina Kościelnicka	2020-04-15	1	-1/+1
*	Reformat so it shows up/looks nice when "help $alu" and "help $alu+"	Eddie Hung	2019-08-09	1	-25/+34
*	A bit more on where $lcu comes from	Eddie Hung	2019-08-09	1	-0/+2
*	Add more comments	Eddie Hung	2019-08-09	1	-4/+18
*	Add a few comments to document $alu and $lcu	Eddie Hung	2019-08-08	1	-9/+12
*	Improve $specrule interface	Clifford Wolf	2019-04-23	1	-2/+2
*	Improve $specrule interface	Clifford Wolf	2019-04-23	1	-3/+4
*	Add $specrule cells for $setup/$hold/$skew specify rules	Clifford Wolf	2019-04-23	1	-0/+28
*	Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom...	Clifford Wolf	2019-04-23	1	-70/+70
*	Add $specify2 and $specify3 cells to simlib	Clifford Wolf	2019-04-23	1	-0/+147
*	Add $allconst and $allseq cell types	Clifford Wolf	2018-02-23	1	-0/+24
*	Add $live and $fair cell types, add support for s_eventually keyword	Clifford Wolf	2017-02-25	1	-0/+16
*	Add $cover cell type and SVA cover() support	Clifford Wolf	2017-02-04	1	-0/+8
*	Added $anyseq cell type	Clifford Wolf	2016-10-14	1	-0/+12
*	Added $global_clock verilog syntax support for creating $ff cells	Clifford Wolf	2016-10-14	1	-2/+6
*	Added $ff and $_FF_ cell types	Clifford Wolf	2016-10-12	1	-0/+13
*	Removed $aconst cell type	Clifford Wolf	2016-08-30	1	-12/+0
*	Removed $predict again	Clifford Wolf	2016-08-28	1	-8/+0
*	Added $anyconst and $aconst	Clifford Wolf	2016-07-27	1	-0/+24
*	Added $initstate cell type and vlog function	Clifford Wolf	2016-07-21	1	-0/+17
*	After reading the SV spec, using non-standard predict() instead of expect()	Clifford Wolf	2016-07-21	1	-9/+1
*	Added basic support for $expect cells	Clifford Wolf	2016-07-13	1	-0/+16
*	Improved support for $sop cells	Clifford Wolf	2016-06-17	1	-3/+3
*	Added $sop cell type and "abc -sop"	Clifford Wolf	2016-06-17	1	-0/+28
*	Added more cell help messages	Clifford Wolf	2016-03-29	1	-0/+73
*	Added read-enable to memory model	Clifford Wolf	2015-09-25	1	-4/+5
*	Added $tribuf and $_TBUF_ sim models	Clifford Wolf	2015-08-16	1	-0/+14
*	Another block of spelling fixes	Larry Doolittle	2015-08-14	1	-2/+2
*	Added WORDS parameter to $meminit	Clifford Wolf	2015-07-31	1	-1/+2
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-2/+2
*	make all vector-size related integer params in $mem sim model signed	Clifford Wolf	2015-04-05	1	-6/+6
*	Added $assume cell type	Clifford Wolf	2015-02-26	1	-1/+18