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path: root/techlibs/common/simlib.v
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* Added WORDS parameter to $meminitClifford Wolf2015-07-311-1/+2
* Fixed trailing whitespacesClifford Wolf2015-07-021-2/+2
* make all vector-size related integer params in $mem sim model signedClifford Wolf2015-04-051-6/+6
* Added $assume cell typeClifford Wolf2015-02-261-1/+18
* Smaller default parameters in $mem simlib modelClifford Wolf2015-02-151-2/+2
* Added $meminit support to "memory" commandClifford Wolf2015-02-141-3/+15
* Added $meminit cell typeClifford Wolf2015-02-141-0/+22
* Some test related fixesClifford Wolf2015-02-121-4/+4
* Added $equiv cell typeClifford Wolf2015-01-191-1/+23
* Progress in memory_bramClifford Wolf2015-01-031-0/+3
* Added proper clkpol support to memory_bramClifford Wolf2015-01-021-1/+1
* New $mem simlib modelClifford Wolf2015-01-021-95/+36
* Fixed simlib entries for $memrd and $memwrClifford Wolf2014-12-301-0/+2
* Added $dffe cell typeClifford Wolf2014-12-081-0/+19
* Fixed $macc simlib model for zero-configClifford Wolf2014-09-161-1/+1
* Fixed simlib $macc model for xilinx xsimClifford Wolf2014-09-081-1/+15
* Simplified $fa undef modelClifford Wolf2014-09-081-1/+1
* Fixes and cleanups for blackbox.vClifford Wolf2014-09-081-68/+70
* Added $lcu cell typeClifford Wolf2014-09-081-0/+23
* Added "$fa" cell typeClifford Wolf2014-09-081-0/+16
* Various bug fixes (related to $macc model testing)Clifford Wolf2014-09-061-1/+1
* Added $macc SAT modelClifford Wolf2014-09-061-3/+3
* Added $macc simlib model (also use as techmap rule for now)Clifford Wolf2014-09-061-0/+86
* Removed $bu0 cell typeClifford Wolf2014-09-041-24/+0
* Undef-related fixes in simlib $alu modelClifford Wolf2014-09-021-3/+6
* Small bug fixes in $not, $neg, and $shiftx modelsClifford Wolf2014-09-021-3/+2
* Fixed "test_cell -simlib all"Clifford Wolf2014-09-011-2/+3
* Added $alu cell typeClifford Wolf2014-08-301-0/+45
* Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-151-11/+11
* RIP $safe_pmuxClifford Wolf2014-08-141-27/+4
* Bugfix in simlib.v for iverilogClifford Wolf2014-07-291-5/+6
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-291-0/+48
* Fixed simlib.v model for $memClifford Wolf2014-07-171-15/+15
* Updated simlib to new $mem/$memwr interfaceClifford Wolf2014-07-161-30/+55
* Added SIMLIB_NOLUT to simlib.vClifford Wolf2014-04-021-0/+2
* Added SIMLIB_NOSR to simlib.vClifford Wolf2014-04-021-0/+6
* Added support for dlatchsr cellsClifford Wolf2014-03-311-0/+32
* Added $slice and $concat cell typesClifford Wolf2014-02-071-0/+30
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-031-13/+47
* More changes to techlibs/common/simlib.v for LECClifford Wolf2014-01-311-6/+11
* Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)Clifford Wolf2014-01-291-105/+305
* Added $assert cellClifford Wolf2014-01-191-0/+15
* Fixed $lut simlib model for a wider range of toolsClifford Wolf2014-01-181-10/+12
* More changes to simlib to make it friendlier to a wider range of toolsClifford Wolf2014-01-181-10/+14
* Fixed a type in $mem model in simlib.vClifford Wolf2014-01-181-1/+1
* Added $bu0 cell to simlib.vClifford Wolf2014-01-181-0/+22
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-271-0/+36
* Renamed stdcells_sim.v to simcells.v and fixed blackbox.vClifford Wolf2013-11-241-8/+8
* Cleanups and bugfixes in response to new internal cell checkerClifford Wolf2013-11-111-6/+7
* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-181-20/+76
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