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| author | Clifford Wolf <clifford@clifford.at> | 2014-12-08 10:50:19 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-12-08 10:50:19 +0100 |
| commit | f1764b4fe99807c445526774563a98224b642766 (patch) | |
| tree | 8acab5d97a8f973b75b258036923b209446a9139 /techlibs/common/simlib.v | |
| parent | fad9cec47b3aa9fc3d413abee92cc8380d0c0dc4 (diff) | |
| download | yosys-f1764b4fe99807c445526774563a98224b642766.tar.gz yosys-f1764b4fe99807c445526774563a98224b642766.tar.bz2 yosys-f1764b4fe99807c445526774563a98224b642766.zip | |
Added $dffe cell type
Diffstat (limited to 'techlibs/common/simlib.v')
| -rw-r--r-- | techlibs/common/simlib.v | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 2d8088adb..e241cd3ce 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1217,6 +1217,25 @@ end endmodule // -------------------------------------------------------- + +module \$dffe (CLK, EN, D, Q); + +parameter WIDTH = 0; +parameter CLK_POLARITY = 1'b1; +parameter EN_POLARITY = 1'b1; + +input CLK, EN; +input [WIDTH-1:0] D; +output reg [WIDTH-1:0] Q; +wire pos_clk = CLK == CLK_POLARITY; + +always @(posedge pos_clk) begin + if (EN == EN_POLARITY) Q <= D; +end + +endmodule + +// -------------------------------------------------------- `ifndef SIMLIB_NOSR module \$dffsr (CLK, SET, CLR, D, Q); |