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common
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Makefile.inc
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Author
Age
Files
Lines
*
techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcu
Eddie Hung
2020-04-03
1
-0
/
+1
*
Create +/abc9_model.v for $__ABC9_{DELAY,FF_}
Eddie Hung
2020-02-27
1
-0
/
+1
*
abc9_ops: -write_box is empty, output a dummy box to prevent ABC error
Eddie Hung
2020-01-15
1
-1
/
+0
*
Makefile: don't assume python is called `python3`
Sean Cross
2019-10-19
1
-2
/
+2
*
Merge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung
2019-09-05
1
-0
/
+1
|
\
|
*
Use a dummy box file if none specified
Eddie Hung
2019-08-28
1
-0
/
+1
*
|
Add mul2dsp multiplier splitting rule and ECP5 mapping
David Shah
2019-07-08
1
-0
/
+1
|
/
*
cmp2lut: new techmap pass.
whitequark
2019-01-02
1
-1
/
+1
*
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.
whitequark
2018-12-05
1
-0
/
+1
*
Add dff2ff.v techmap file
Clifford Wolf
2017-05-31
1
-0
/
+1
*
Added "prep" command
Clifford Wolf
2015-10-14
1
-0
/
+1
*
Added first help messages for cell types
Clifford Wolf
2015-10-14
1
-0
/
+15
*
Adjust makefiles to work with out-of-tree builds
Clifford Wolf
2015-08-12
1
-7
/
+0
*
Added cells.lib
Clifford Wolf
2015-01-16
1
-0
/
+1
*
Added add_share_file Makefile macro
Clifford Wolf
2015-01-08
1
-25
/
+6
*
Fixed build with SMALL=1
Clifford Wolf
2014-12-30
1
-0
/
+2
*
Added "synth" command
Clifford Wolf
2014-09-14
1
-0
/
+2
*
Added adff2dff.v (for techmap -share_map)
Clifford Wolf
2014-08-07
1
-1
/
+5
*
Renamed "stdcells.v" to "techmap.v"
Clifford Wolf
2014-07-31
1
-1
/
+5
*
Added "make PRETTY=1"
Clifford Wolf
2014-07-24
1
-10
/
+10
*
Merged addition of SED makefile variable from github.com/Siesh1oo/yosys
Clifford Wolf
2014-03-11
1
-1
/
+1
*
Added techlibs/common/pmux2mux.v
Clifford Wolf
2014-01-17
1
-1
/
+5
*
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
Clifford Wolf
2013-11-24
1
-3
/
+11
*
Install simlib in datdir
Clifford Wolf
2013-11-19
1
-0
/
+6
*
Moved common techlib files to techlibs/common
Clifford Wolf
2013-09-15
1
-0
/
+7