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* Cleanup +/cmp2lut.vEddie Hung2020-04-031-8/+0
* synth_xilinx: techmap +/cmp2lut.v and +/cmp2lcu.v in 'coarse'Eddie Hung2020-04-031-2/+1
* +/cmp2lcu.v to work efficiently for fully/partially constant inputsEddie Hung2020-04-031-33/+42
* +/cmp2lcu.v to work efficiently for fully/partially constant inputsEddie Hung2020-04-031-3/+31
* Refactor +/cmp2lcu.v into recursive techmapEddie Hung2020-04-032-39/+66
* CleanupEddie Hung2020-04-031-31/+28
* Cleanup cmp2lcu.vEddie Hung2020-04-031-16/+16
* techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcuEddie Hung2020-04-033-0/+108
* cmp2lut: comment out unused since 362f4f9Eddie Hung2020-04-031-8/+8
* Merge pull request #1845 from YosysHQ/eddie/kernel_speedupEddie Hung2020-04-0220-588/+566
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| * kernel: pass-by-value into Design::scratchpad_set_string() tooEddie Hung2020-03-272-3/+3
| * kernel: const Wire* overload -> Wire* !!!Eddie Hung2020-03-261-1/+1
| * kernel: Cell::set{Port,Param}() to pass by value, but use std::moveEddie Hung2020-03-262-7/+7
| * kernel: SigSpec copies to not trigger pack()Eddie Hung2020-03-182-34/+5
| * kernel: more pass by const ref, more speedupsEddie Hung2020-03-187-400/+400
| * kernel: speedupEddie Hung2020-03-181-30/+23
| * kernel: use const reference for SigSet tooEddie Hung2020-03-171-18/+18
| * kernel: fix DeleteWireWorkerEddie Hung2020-03-171-9/+4
| * kernel: SigSpec use more const& + overloads to prevent implicit SigSpecEddie Hung2020-03-1314-82/+96
| * kernel: optimise Module::remove(const pool<RTLIL::Wire*>()Eddie Hung2020-03-122-10/+9
| * kernel: SigPool to use const& + overloads to prevent implicit SigSpecEddie Hung2020-03-121-19/+25
* | Bump YOSYS_VERClaire Wolf2020-04-021-1/+1
* | Merge pull request #1770 from YosysHQ/claire/btor_symbolsClaire Wolf2020-04-021-36/+60
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| * | Improve write_btor symbol handlingClaire Wolf2020-03-141-36/+60
* | | Merge pull request #1765 from YosysHQ/claire/btor_infoClaire Wolf2020-04-021-9/+113
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| * | Add info-file and cover features to write_btorClaire Wolf2020-03-131-9/+113
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* | Merge pull request #1777 from YosysHQ/claire/manyhotClaire Wolf2020-04-021-14/+146
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| * | Improve ezsat onehot encoding schemeClaire Wolf2020-04-021-14/+28
| * | Using LFSR counter for ezSAT::manyhot()Claire Wolf2020-04-021-0/+118
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* | Merge pull request #1828 from YosysHQ/eddie/celltypes_speedupEddie Hung2020-04-014-31/+50
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| * | memory_share: fix stray braceEddie Hung2020-03-301-1/+0
| * | Code review fixesEddie Hung2020-03-302-3/+3
| * | Apply suggestions from code reviewEddie Hung2020-03-302-6/+2
| * | kernel: clear some more ShareWorker stateEddie Hung2020-03-261-0/+4
| * | kernel: share a single CellTypes within a passEddie Hung2020-03-184-31/+51
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* | Merge pull request #1790 from YosysHQ/eddie/opt_expr_xorEddie Hung2020-04-014-10/+92
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| * | opt_expr: fix failing $xnor testEddie Hung2020-03-201-2/+17
| * | opt_expr: add failing $xnor testEddie Hung2020-03-201-1/+13
| * | Simplify breaking tests/arch/*/fsm.ys testsEddie Hung2020-03-202-7/+3
| * | opt_expr: fix missing braceEddie Hung2020-03-201-2/+4
| * | opt_expr: add $xor/$xnor/$_XOR_/$_XNOR_ testsEddie Hung2020-03-191-0/+40
| * | opt_expr: extend to $xnor and $_XNOR_Eddie Hung2020-03-191-8/+12
| * | opt_expr: optimise 1-bit $xor or $_XOR_ with constant inputEddie Hung2020-03-191-1/+14
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* | Merge pull request #1789 from YosysHQ/eddie/opt_expr_aluEddie Hung2020-04-012-19/+114
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| * | opt_expr: add $alu testsEddie Hung2020-03-191-0/+63
| * | opt_expr: remove redundantEddie Hung2020-03-191-3/+0
| * | opt_expr: optimise $sub when both A[i] and B[i] == 1'b1Eddie Hung2020-03-191-9/+20
| * | opt_expr: optimise for identity $alu-s just like $add/$subEddie Hung2020-03-191-7/+31
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* | Merge pull request #1844 from YosysHQ/dave/gen-source-locDavid Shah2020-04-011-0/+6
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| * | verilog: Add location info for generate constructsDavid Shah2020-04-011-0/+6
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