| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | anlogic: implement DRAM initialization | Icenowy Zheng | 2018-12-20 | 1 | -1/+4 |
| | | | | | | | | | | | | As the TD tool doesn't accept the DRAM cell to contain unknown values in the initial value, the initialzation support of DRAM is previously skipped. Now add the support by add a new pass to determine unknown values in the initial value. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> | ||||
| * | anlogic: add support for Eagle Distributed RAM | Icenowy Zheng | 2018-12-17 | 1 | -0/+19 |
| The MSLICEs on the Eagle series of FPGA can be configured as Distributed RAM. Enable to synthesis to DRAM. As the Anlogic software suite doesn't support any 'bx to exist in the initializtion data of DRAM, do not enable the initialization support of the inferred DRAM. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> | |||||
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index : iCE40/yosys | |
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