diff options
| author | Icenowy Zheng <icenowy@aosc.io> | 2018-12-19 10:18:47 +0800 |
|---|---|---|
| committer | Icenowy Zheng <icenowy@aosc.io> | 2018-12-20 07:56:15 +0800 |
| commit | 90d00182cfe358438d777f2ca7abacb4c6a2733c (patch) | |
| tree | 5af285a46aa934a6b8b3a1aa316a26983a1054f4 /techlibs/anlogic/drams_map.v | |
| parent | 93d44bb9a613b46a80642b8ce71295db18fadbc5 (diff) | |
| download | yosys-90d00182cfe358438d777f2ca7abacb4c6a2733c.tar.gz yosys-90d00182cfe358438d777f2ca7abacb4c6a2733c.tar.bz2 yosys-90d00182cfe358438d777f2ca7abacb4c6a2733c.zip | |
anlogic: implement DRAM initialization
As the TD tool doesn't accept the DRAM cell to contain unknown values in
the initial value, the initialzation support of DRAM is previously
skipped.
Now add the support by add a new pass to determine unknown values in the
initial value.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Diffstat (limited to 'techlibs/anlogic/drams_map.v')
| -rw-r--r-- | techlibs/anlogic/drams_map.v | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/techlibs/anlogic/drams_map.v b/techlibs/anlogic/drams_map.v index 87cbb6a45..084e2a25f 100644 --- a/techlibs/anlogic/drams_map.v +++ b/techlibs/anlogic/drams_map.v @@ -1,4 +1,5 @@ module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [63:0]INIT = 64'bx; input CLK1; input [3:0] A1ADDR; @@ -8,7 +9,9 @@ module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); input [3:0] B1DATA; input B1EN; - EG_LOGIC_DRAM16X4 _TECHMAP_REPLACE_ ( + EG_LOGIC_DRAM16X4 #( + `include "dram_init_16x4.vh" + ) _TECHMAP_REPLACE_ ( .di(B1DATA), .waddr(B1ADDR), .wclk(CLK1), |