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| author | Icenowy Zheng <icenowy@aosc.io> | 2018-12-14 16:50:37 +0800 |
|---|---|---|
| committer | Icenowy Zheng <icenowy@aosc.io> | 2018-12-17 23:20:40 +0800 |
| commit | d53a2bd1d3ae3cfbc9ead0fc12999fe269628179 (patch) | |
| tree | e1381a28a5bcf902221a7a5e7016f342187e934c /techlibs/anlogic/drams_map.v | |
| parent | 634d7d1c1424c69d983c008cfd800c0d7db43379 (diff) | |
| download | yosys-d53a2bd1d3ae3cfbc9ead0fc12999fe269628179.tar.gz yosys-d53a2bd1d3ae3cfbc9ead0fc12999fe269628179.tar.bz2 yosys-d53a2bd1d3ae3cfbc9ead0fc12999fe269628179.zip | |
anlogic: add support for Eagle Distributed RAM
The MSLICEs on the Eagle series of FPGA can be configured as Distributed
RAM.
Enable to synthesis to DRAM.
As the Anlogic software suite doesn't support any 'bx to exist in the
initializtion data of DRAM, do not enable the initialization support of
the inferred DRAM.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Diffstat (limited to 'techlibs/anlogic/drams_map.v')
| -rw-r--r-- | techlibs/anlogic/drams_map.v | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/techlibs/anlogic/drams_map.v b/techlibs/anlogic/drams_map.v new file mode 100644 index 000000000..87cbb6a45 --- /dev/null +++ b/techlibs/anlogic/drams_map.v @@ -0,0 +1,19 @@ +module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + input CLK1; + + input [3:0] A1ADDR; + output [3:0] A1DATA; + + input [3:0] B1ADDR; + input [3:0] B1DATA; + input B1EN; + + EG_LOGIC_DRAM16X4 _TECHMAP_REPLACE_ ( + .di(B1DATA), + .waddr(B1ADDR), + .wclk(CLK1), + .we(B1EN), + .raddr(A1ADDR), + .do(A1DATA) + ); +endmodule |