iCE40/yosys - clone of https://github.com/YosysHQ/yosys

	Commit message (Expand)	Author	Age	Files	Lines
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* \| \| \|	Merge pull request #735 from daveshah1/trifixes	Clifford Wolf	2018-12-16	1	-3/+4
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\| * \| \| \|	deminout: Consider $tribuf cells	David Shah	2018-12-12	1	-2/+2
\| * \| \| \|	deminout: Don't demote constant-driven inouts to inputs	David Shah	2018-12-12	1	-1/+2
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* \| \| \|	Fix equiv_opt indenting	Clifford Wolf	2018-12-16	1	-139/+129
* \| \| \|	Merge pull request #724 from whitequark/equiv_opt	Clifford Wolf	2018-12-16	2	-1/+168
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\| * \| \| \|	equiv_opt: pass -D EQUIV when techmapping.	whitequark	2018-12-07	1	-2/+4
\| * \| \| \|	equiv_opt: new command, for verifying optimization passes.	whitequark	2018-12-07	2	-1/+166
* \| \| \| \|	Merge pull request #734 from grahamedgecombe/fix-shuffled-bram-initdata	Clifford Wolf	2018-12-16	1	-0/+17
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\| * \| \| \| \|	memory_bram: Fix initdata bit order after shuffling	Graham Edgecombe	2018-12-11	1	-0/+17
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* \| \| \| \|	Merge pull request #714 from daveshah1/abc_preserve_naming	Clifford Wolf	2018-12-16	1	-29/+51
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\| * \| \| \| \|	abc: Preserve naming through ABC using 'dress' command	David Shah	2018-12-06	1	-29/+51
* \| \| \| \| \|	Merge pull request #722 from whitequark/rename_src	Clifford Wolf	2018-12-16	1	-0/+50
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\| * \| \| \| \| \|	rename: add -src, for inferring names from source locations.	whitequark	2018-12-05	1	-0/+50
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* \| \| \| \| \|	Merge pull request #720 from whitequark/master	Clifford Wolf	2018-12-16	2	-2/+2
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\| * \| \| \| \|	lut2mux: handle 1-bit INIT constant in $lut cells.	whitequark	2018-12-05	1	-1/+1
\| * \| \| \| \|	opt_lut: simplify type conversion. NFC.	whitequark	2018-12-05	1	-1/+1
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* \| \| \| \|	opt_lut: leave intact LUTs with cascade feeding module outputs.	whitequark	2018-12-07	1	-0/+6
* \| \| \| \|	opt_lut: show original truth table for both cells.	whitequark	2018-12-07	1	-2/+3
* \| \| \| \|	opt_lut: add -limit option, for debugging misoptimizations.	whitequark	2018-12-07	1	-3/+21
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* \| \| \|	Bugfix in opt_expr handling of a<0 and a>=0	Clifford Wolf	2018-12-06	1	-1/+1
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* \| \|	Rename opt_lut.cpp to opt_lut.cc	Clifford Wolf	2018-12-05	1	-0/+0
* \| \|	opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.	whitequark	2018-12-05	1	-17/+163
* \| \|	opt_lut: always prefer to eliminate 1-LUTs.	whitequark	2018-12-05	1	-19/+41
* \| \|	opt_lut: collect and display statistics.	whitequark	2018-12-05	1	-4/+33
* \| \|	opt_lut: refactor to use a worker. NFC.	whitequark	2018-12-05	1	-170/+177
* \| \|	opt_lut: new pass, to combine LUTs for tighter packing.	whitequark	2018-12-05	2	-0/+275
* \| \|	Fix typo	Clifford Wolf	2018-12-04	1	-1/+1
* \| \|	Merge pull request #702 from smunaut/min_ce_use	Clifford Wolf	2018-12-04	1	-1/+36
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\| * \| \|	dff2dffe: Add option for unmap to only remove DFFE with low CE signal use	Sylvain Munaut	2018-11-27	1	-1/+36
* \| \| \|	Merge pull request #676 from rafaeltp/master	Clifford Wolf	2018-12-01	1	-10/+17
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\| * \| \|	using [i] to access individual bits of SigSpec and merging bits into a tmp Si...	rafaeltp	2018-10-21	1	-11/+12
\| * \| \|	cleaning up for PR	rafaeltp	2018-10-20	1	-2/+2
\| * \| \|	fixing code style	rafaeltp	2018-10-20	1	-1/+1
\| * \| \|	solves #675	rafaeltp	2018-10-20	1	-11/+17
* \| \| \|	Add iteration limit to "opt_muxtree"	Clifford Wolf	2018-11-20	1	-1/+17
* \| \| \|	DFFLIBMAP: changed 'missing pin' error into a warning with additional reason/...	Niels Moseley	2018-11-06	1	-1/+10
* \| \| \|	Allow square brackets in liberty identifiers	Clifford Wolf	2018-11-05	1	-2/+2
* \| \| \|	Liberty file newline handling is more relaxed. More descriptive error message	Niels Moseley	2018-11-03	1	-4/+7
* \| \| \|	Report an error when a liberty file contains pin references that reference no...	Niels Moseley	2018-11-03	1	-0/+3
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* \| \|	Refactor code to avoid code duplication + added comments	Ruben Undheim	2018-10-20	1	-2/+5
* \| \|	Support for SystemVerilog interfaces as a port in the top level module + test...	Ruben Undheim	2018-10-20	1	-5/+36
* \| \|	Merge pull request #672 from daveshah1/fix_bram	Clifford Wolf	2018-10-19	1	-0/+1
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\| * \| \|	memory_bram: Reset make_outreg when growing read ports	David Shah	2018-10-19	1	-0/+1
* \| \| \|	Merge pull request #659 from rubund/sv_interfaces	Clifford Wolf	2018-10-18	1	-7/+188
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\| * \| \| \|	Documentation improvements etc.	Ruben Undheim	2018-10-13	1	-27/+38
\| * \| \| \|	Support for 'modports' for System Verilog interfaces	Ruben Undheim	2018-10-12	1	-1/+13
\| * \| \| \|	Synthesis support for SystemVerilog interfaces	Ruben Undheim	2018-10-12	1	-7/+165
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* \| \| \|	stop check_signal_in_fanout from traversing FFs	tklam	2018-10-13	1	-2/+2
* \| \| \|	stop check_signal_in_fanout from traversing FFs	tklam	2018-10-13	1	-1/+12
* \| \| \|	fix bug: pass by reference	tklam	2018-09-26	1	-1/+1