diff options
| author | tklam <tklam@easylogic.hk> | 2018-10-13 23:11:19 +0800 |
|---|---|---|
| committer | tklam <tklam@easylogic.hk> | 2018-10-13 23:11:19 +0800 |
| commit | 302edf04291467469f8f48bd60edadbf1ee54798 (patch) | |
| tree | 7068763ae9f27dc5e92a4add130415d0c001ddd4 /passes | |
| parent | 3c5406c31b416bccb5cc98398b7e5a77d017a138 (diff) | |
| download | yosys-302edf04291467469f8f48bd60edadbf1ee54798.tar.gz yosys-302edf04291467469f8f48bd60edadbf1ee54798.tar.bz2 yosys-302edf04291467469f8f48bd60edadbf1ee54798.zip | |
stop check_signal_in_fanout from traversing FFs
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/equiv/equiv_make.cc | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index e74dab36f..e75482e9f 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -42,6 +42,14 @@ struct EquivMakeWorker dict<SigBit, pool<Cell*>> bit2driven; // map: bit <--> and its driven cells + CellTypes comb_ct; + + EquivMakeWorker() + { + comb_ct.setup_internals(); + comb_ct.setup_stdcells(); + } + void read_blacklists() { for (auto fn : blacklists) @@ -415,9 +423,12 @@ struct EquivMakeWorker auto driven_cells = bit2driven.at(source_bit); for (auto driven_cell: driven_cells) { - if (visited_cells.count(driven_cell) > 0) + bool is_comb = comb_ct.cell_known(cell->type); + if (is_comb) continue; + if (visited_cells.count(driven_cell) > 0) + continue; visited_cells.insert(driven_cell); for (auto &conn: driven_cell->connections()) |