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* abc9_ops: Don't leave unused derived modules lying aroundgatecat2022-05-231-0/+9
* select: Fix -assert-none and -assert-any error output and docsJannis Harder2022-05-191-8/+10
* Add memory_bmux2rom pass.Marcelina Kościelnicka2022-05-183-1/+97
* Add memory_libmap pass.Marcelina Kościelnicka2022-05-185-0/+3872
* proc_rom: Add special handling of const-0 address bits.Marcelina Kościelnicka2022-05-181-15/+40
* opt_ffinv: Use ModIndex instead of ModWalker.Marcelina Kościelnicka2022-05-171-50/+53
* Add opt_ffinv pass.Marcelina Kościelnicka2022-05-132-0/+256
* Add proc_rom pass.Marcelina Kościelnicka2022-05-133-0/+239
* Merge pull request #3299 from YosysHQ/mmicko/sim_memoryMiodrag Milanović2022-05-091-2/+18
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| * fix crash when no fst inputMiodrag Milanovic2022-05-041-1/+2
| * Start restoring memory state from VCD/FSTMiodrag Milanovic2022-05-041-2/+17
* | opt_mem: Remove constant-value bit lanes.Marcelina Kościelnicka2022-05-071-13/+143
* | memory_share: fix wrong argidx in extra_argsimhcyx2022-05-051-1/+1
* | abc: Use dict/pool instead of std::map/std::setMarcelina Kościelnicka2022-05-041-14/+14
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* AIM file could have gaps in or between inputs and initsMiodrag Milanovic2022-05-021-3/+6
* Merge pull request #3257 from jix/tribuf-formalJannis Harder2022-04-251-3/+46
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| * tribuf: `-formal` option: convert all to logic and detect conflictsJannis Harder2022-04-121-3/+46
* | Match $anyseq input if connected to public wireMiodrag Milanovic2022-04-221-6/+12
* | Treat $anyseq as input from FSTMiodrag Milanovic2022-04-221-0/+21
* | Last sample from input does not represent changeMiodrag Milanovic2022-04-221-1/+2
* | latches are always set to zeroMiodrag Milanovic2022-04-221-6/+1
* | If not multiclock, output only on clock edgesMiodrag Milanovic2022-04-221-0/+18
* | Set init state for all wires from FST and set pastMiodrag Milanovic2022-04-221-13/+12
* | Fix multiclock for btor2 witnessMiodrag Milanovic2022-04-221-5/+9
* | Merge pull request #3280 from YosysHQ/micko/fix_readaiwMiodrag Milanović2022-04-181-2/+2
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| * | Fix reading aiw from other solversMiodrag Milanovic2022-04-151-2/+2
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* | memory_share: Fix up mismatched address widths.Marcelina Kościelnicka2022-04-151-0/+14
* | opt_dff: Fix behavior on $ff with D == Q.Marcelina Kościelnicka2022-04-151-1/+1
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* Use wrap_async_control_gate if ff is fineMiodrag Milanovic2022-04-081-9/+11
* Makefile: properly conditionalize features requiring compression.Iris Johnson2022-04-071-0/+2
* Merge pull request #3269 from YosysHQ/micko/fix_autotopCatherine2022-04-071-13/+13
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| * Reorder steps in -auto-top to fix synth command, fixes #3261Miodrag Milanovic2022-04-051-13/+13
* | abc: Add support for FFs with reset in -dffMarcelina Kościelnicka2022-04-071-90/+229
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* show: Fix width labels.Marcelina Kościelnicka2022-04-041-23/+18
* past_ad initial value settingMiodrag Milanovic2022-04-021-0/+3
* setInitState can be only one altering valuesMiodrag Milanovic2022-04-021-4/+6
* Set past_d value for init stateMiodrag Milanovic2022-04-021-0/+2
* Merge pull request #3264 from jix/invalid_ff_dcinit_mergeJannis Harder2022-04-022-2/+21
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| * opt_merge: Add `-keepdc` option required for formal verificationJannis Harder2022-04-012-2/+21
* | Set init values for wrapped async control signalsMiodrag Milanovic2022-04-011-0/+2
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* Support memories in aiw and multiclockMiodrag Milanovic2022-03-311-16/+86
* Merge pull request #3194 from Ravenslofty/abc9-flow3mfsLofty2022-03-281-1/+7
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| * abc9: add flow3mfs scriptLofty2022-02-101-1/+7
* | abc9_ops: Also derive blackboxes with timing infogatecat2022-03-241-5/+10
* | Proper SigBit forming in simMiodrag Milanovic2022-03-221-4/+4
* | Proper SigBit forming in simMiodrag Milanovic2022-03-221-4/+4
* | More verbose warningsMiodrag Milanovic2022-03-181-5/+7
* | Recognize registers and set initial state for them in tbMiodrag Milanovic2022-03-161-6/+32
* | Update sim help message.Miodrag Milanovic2022-03-161-1/+2
* | Merge pull request #3232 from YosysHQ/micko/fst2tbMiodrag Milanović2022-03-141-0/+319
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