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* simplemap: refactor to use FfData.Marcelina Kościelnicka2021-10-022-287/+20
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* abc9: make re-entrant (#2993)Eddie Hung2021-09-092-9/+9
| | | | | | | | | * Add testcase * Cleanup some state at end of abc9 * Re-assign abc9_box_id from scratch * Suppress delete unless prep_bypass did something
* abc9: holes module to instantiate cells with NEW_ID (#2992)Eddie Hung2021-09-091-1/+1
| | | | | * Add testcase * holes module to instantiate cells with NEW_ID
* abc9: replace cell type/parameters if derived type already processed (#2991)Eddie Hung2021-09-091-6/+22
| | | | | | | | | | | * Add close bracket * Add testcase * Replace cell type/param if in unmap_design * Improve abc9_box error message too * Update comment as per review
* opt_merge: Remove and reinsert init when connecting nets.Marcelina Kościelnicka2021-08-221-3/+4
| | | | | | | | Mutating the SigMap by adding a new connection will throw off FfInitVals index. Work around this by removing the relevant init values from index whenever we connect nets, then re-add the new init value. Should fix #2920.
* opt_clean: Make the init attribute follow the FF's Q.Marcelina Kościelnicka2021-08-221-0/+24
| | | | | | | | | | Previously, opt_clean would reconnect all ports (including FF Q ports) to a "canonical" SigBit chosen by complex rules, but would leave the init attribute on the old wire. This change applies the same canonicalization rules to the init attributes, ensuring that init moves to wherever the Q port moved. Part of another jab at #2920.
* proc_prune: Make assign removal and promotion per-bit, remember promoted bits.Marcelina Kościelnicka2021-08-141-40/+25
| | | | Fixes #2962.
* Add opt_mem_widen pass.Marcelina Kościelnicka2021-08-143-0/+110
| | | | If all of us are wide, then none of us are!
* memory_share: Add -nosat and -nowiden options.Marcelina Kościelnicka2021-08-142-10/+41
| | | | This unlocks wide port recognition by default.
* memory_dff: Recognize soft transparency logic.Marcelina Kościelnicka2021-08-131-7/+451
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* Add new opt_mem_priority pass.Marcelina Kościelnicka2021-08-133-2/+114
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* Merge pull request #2932 from YosysHQ/mwk/logger-check-expectedMiodrag Milanović2021-08-131-0/+9
|\ | | | | logger: Add -check-expected subcommand.
| * logger: Add -check-expected subcommand.Marcelina Kościelnicka2021-08-121-0/+9
| | | | | | | | | | This allows us to have multiple "expect this warning" calls in a single long script, covering only as many passes as necessary.
* | memory_share: Pass addresses through sigmap_xmux everywhere.Marcelina Kościelnicka2021-08-131-20/+25
|/ | | | This fixes wide port recognition in some cases.
* memory_dff: Recognize read ports with reset / initial value.Marcelina Kościelnicka2021-08-111-7/+0
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* proc_memwr: Use the v2 memwr cell.Marcelina Kościelnicka2021-08-111-9/+19
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* Add v2 memory cells.Marcelina Kościelnicka2021-08-117-10/+14
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* kernel/mem: Introduce transparency masks.Marcelina Kościelnicka2021-08-114-70/+45
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* Refactor common parts of SAT-using optimizations into a helper.Marcelina Kościelnicka2021-08-093-150/+40
| | | | | | | | | | | | | This also aligns the functionality: - in all cases, the onehot attribute is used to create appropriate constraints (previously, opt_dff didn't do it at all, and share created one-hot constraints based on $pmux presence alone, which is unsound) - in all cases, shift and mul/div/pow cells are now skipped when importing the SAT problem (previously only memory_share did this) — this avoids creating clauses for hard cells that are unlikely to help with proving the UNSATness needed for optimization
* opt_merge: Use FfInitVals.Marcelina Kościelnicka2021-08-081-27/+8
| | | | Partial #2920 fix.
* memory_share: Don't skip ports with EN wired to input for SAT sharing.Marcelina Kościelnicka2021-08-041-3/+1
| | | | Fixes #2912.
* memory_bram: Move init data swizzling before other swizzling.Marcelina Kościelnicka2021-08-031-18/+18
| | | | Fixes #2907.
* memory_bram: Some refactoringMarcelina Kościelnicka2021-08-011-196/+174
| | | | | | This will make more sense when the new transparency masks land. Fixes #2902.
* proc_rmdead: use explicit pattern set when there are no wildcardsZachary Snow2021-07-291-2/+63
| | | | | | | | If width of a case expression was large, explicit patterns could cause the existing logic to take an extremely long time, or exhaust the maximum size of the underlying set. For cases where all of the patterns are fully defined and there are no constants in the case expression, this change uses a simple set to track which patterns have been seen.
* opt_lut: Allow more than one -dlogic per cell type.Marcelina Kościelnicka2021-07-291-23/+30
| | | | Fixes #2061.
* memory: Introduce $meminit_v2 cell, with EN input.Marcelina Kościelnicka2021-07-283-2/+3
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* proc: Run opt_expr at the endMarcelina Kościelnicka2021-07-271-0/+11
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* opt_expr: Propagate constants to port connections.Marcelina Kościelnicka2021-07-271-3/+22
| | | | | | | | This adds one simple piece of functionality to opt_expr: when a cell port is connected to a fully-constant signal (as determined by sigmap), the port is reconnected directly to the constant value. This is just enough optimization to fix the "non-constant $meminit input" problem without requiring a full opt_clean or a separate pass.
* Use new read_id_num helper function elsewhere in hierarchy.ccRupert Swarbrick2021-07-201-5/+6
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* Extract connection checking logic from expand_module in hierarchy.ccRupert Swarbrick2021-07-201-23/+64
| | | | | No functional change, but pulls more logic out of the expand_module function.
* Extract missing module support in hierarchy.cc to a helper functionRupert Swarbrick2021-07-141-44/+68
| | | | | | | | | | I think the code is now a bit easier to follow (and has lost some levels of indentation!). The only non-trivial change is that I removed the check for cell->type[0] != '$' when deciding whether to complain if we couldn't find a module. This will always be true because of the early exit earlier in the function.
* Delete unused found_init variableRupert Swarbrick2021-07-141-3/+0
| | | | | | | Spotted during compilation: passes/proc/proc_init.cc: In function ‘void {anonymous}::proc_init(Yosys::RTLIL::Module*, Yosys::SigMap&, Yosys::RTLIL::Process*)’: passes/proc/proc_init.cc:31:7: warning: variable ‘found_init’ set but not used [-Wunused-but-set-variable]
* rtlil: Make Process handling more uniform with Cell and Wire.Marcelina Kościelnicka2021-07-123-16/+12
| | | | | | - add a backlink to module from Process - make constructor and destructor protected, expose Module functions to add and remove processes
* Move interface expansion in hierarchy.cc into a helper classRupert Swarbrick2021-06-161-100/+189
| | | | | | | | | | | | There should be no functional change, but this splits up the control flow across functions, using class fields to hold the state that's being tracked. The result should be a bit easier to read. This is part of work to add bind support, but I'm doing some refactoring in the hierarchy pass to make the code a bit easier to work with. The idea is that (eventually) the IFExpander object will hold all the logic for expanding interfaces, and then other code can do bind insertion.
* opt_muxtree: Update port_off and port_idx even for constant bitsgatecat2021-06-111-17/+16
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits.Marcelina Kościelnicka2021-06-091-122/+85
| | | | | The previous code, in addition to being needlessly limitted to 32 bits in the first place, also had UB for the 31th bit (doing 1 << 31).
* opt_expr: Optimize div/mod by const 1.Marcelina Kościelnicka2021-06-091-4/+4
| | | | | | | | Turns out the code for div by a power of 2 is already almost capable of optimizing this to a shift-by-0 or and-with-0, which will be further folded into nothingness; let's beef it up to handle div by 1 as well. Fixes #2820.
* Merge pull request #2817 from YosysHQ/claire/fixemailsClaire Xen2021-06-09149-154/+154
|\ | | | | Fixing old e-mail addresses and deadnames
| * Fix deadname SVN linksClaire Xenia Wolf2021-06-092-3/+3
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * Use HTTPS for website links, gatecat emailClaire Xenia Wolf2021-06-091-1/+1
| | | | | | | | | | | | | | | | | | | | git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g;
| * Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-08149-151/+151
| | | | | | | | | | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* | autoname: simple perf optimizationsZachary Snow2021-06-081-11/+15
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* memory_map: Improve start_offset handling.Marcelina Kościelnicka2021-05-311-35/+31
| | | | Fixes #2775.
* memory_share: Add read port merging.Marcelina Kościelnicka2021-05-291-0/+140
| | | | | This is mostly meant for wide port recognition, but may also happen to merge some ports with compatible initial/reset values (eg. 0 vs x).
* memory_share: Improve sat-based port sharing.Marcelina Kościelnicka2021-05-281-117/+151
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* Make a few passes auto-call Mem::narrow instead of rejecting wide ports.Marcelina Kościelnicka2021-05-281-14/+1
| | | | | | This essentially adds wide port support for free in passes that don't have a usefully better way of handling wide ports than just breaking them up to narrow ports, avoiding "please run memory_narrow" annoyance.
* memory_share: Improve same-address merging, recognize wide write ports.Marcelina Kościelnicka2021-05-271-204/+77
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* kernel/mem: Add sub_addr helpers.Marcelina Kościelnicka2021-05-261-6/+2
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* mem/extract_rdff: Fix "no FF made" edge case.Marcelina Kościelnicka2021-05-251-2/+5
| | | | | | | When converting a sync transparent read port with const address to async read port, nothing at all needs to be done other than clk_enable change, and thus we have no FF cell to return. Handle this case correctly in the helper and in its users.
* memory_bram: Reuse extract_rdff helper for make_outreg.Marcelina Kościelnicka2021-05-251-23/+38
| | | | | Also properly skip read ports with init value or reset when not making use of make_outreg. Proper support for matching those will land later.
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