| Commit message (Expand) | Author | Age | Files | Lines | ||
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| * | | | opt_dff: Fix behavior on $ff with D == Q. | Marcelina Kościelnicka | 2022-04-15 | 1 | -1/+1 | |
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| * | | Use wrap_async_control_gate if ff is fine | Miodrag Milanovic | 2022-04-08 | 1 | -9/+11 | |
| * | | Makefile: properly conditionalize features requiring compression. | Iris Johnson | 2022-04-07 | 1 | -0/+2 | |
| * | | Merge pull request #3269 from YosysHQ/micko/fix_autotop | Catherine | 2022-04-07 | 1 | -13/+13 | |
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| | * | | Reorder steps in -auto-top to fix synth command, fixes #3261 | Miodrag Milanovic | 2022-04-05 | 1 | -13/+13 | |
| * | | | abc: Add support for FFs with reset in -dff | Marcelina Kościelnicka | 2022-04-07 | 1 | -90/+229 | |
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| * | | show: Fix width labels. | Marcelina Kościelnicka | 2022-04-04 | 1 | -23/+18 | |
| * | | past_ad initial value setting | Miodrag Milanovic | 2022-04-02 | 1 | -0/+3 | |
| * | | setInitState can be only one altering values | Miodrag Milanovic | 2022-04-02 | 1 | -4/+6 | |
| * | | Set past_d value for init state | Miodrag Milanovic | 2022-04-02 | 1 | -0/+2 | |
| * | | Merge pull request #3264 from jix/invalid_ff_dcinit_merge | Jannis Harder | 2022-04-02 | 2 | -2/+21 | |
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| | * | | opt_merge: Add `-keepdc` option required for formal verification | Jannis Harder | 2022-04-01 | 2 | -2/+21 | |
| * | | | Set init values for wrapped async control signals | Miodrag Milanovic | 2022-04-01 | 1 | -0/+2 | |
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| * | | Support memories in aiw and multiclock | Miodrag Milanovic | 2022-03-31 | 1 | -16/+86 | |
| * | | Merge pull request #3194 from Ravenslofty/abc9-flow3mfs | Lofty | 2022-03-28 | 1 | -1/+7 | |
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| | * | | abc9: add flow3mfs script | Lofty | 2022-02-10 | 1 | -1/+7 | |
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| * | | abc9_ops: Also derive blackboxes with timing info | gatecat | 2022-03-24 | 1 | -5/+10 | |
| * | | Proper SigBit forming in sim | Miodrag Milanovic | 2022-03-22 | 1 | -4/+4 | |
| * | | Proper SigBit forming in sim | Miodrag Milanovic | 2022-03-22 | 1 | -4/+4 | |
| * | | More verbose warnings | Miodrag Milanovic | 2022-03-18 | 1 | -5/+7 | |
| * | | Recognize registers and set initial state for them in tb | Miodrag Milanovic | 2022-03-16 | 1 | -6/+32 | |
| * | | Update sim help message. | Miodrag Milanovic | 2022-03-16 | 1 | -1/+2 | |
| * | | Merge pull request #3232 from YosysHQ/micko/fst2tb | Miodrag Milanović | 2022-03-14 | 1 | -0/+319 | |
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| | * | | Added fst2tb pass for generating testbench | Miodrag Milanovic | 2022-03-14 | 1 | -0/+319 | |
| * | | | Merge pull request #3213 from antonblanchard/abc-typo | Claire Xen | 2022-03-14 | 1 | -2/+2 | |
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| | * | | abc: Fix {I} and {P} substitution | Anton Blanchard | 2022-02-23 | 1 | -2/+2 | |
| * | | | Merge pull request #3229 from YosysHQ/micko/sim_date | Miodrag Milanović | 2022-03-11 | 1 | -7/+20 | |
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| | * | | | Add date parameter to enable full date/time and version info | Miodrag Milanovic | 2022-03-11 | 1 | -7/+20 | |
| * | | | | Add "sim -q" option | Claire Xenia Wolf | 2022-03-11 | 1 | -8/+19 | |
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| * | | | Small fix in "sim" help message | Claire Xenia Wolf | 2022-03-11 | 1 | -1/+1 | |
| * | | | FstData already do conversion to VCD | Miodrag Milanovic | 2022-03-11 | 1 | -1/+2 | |
| * | | | Support cell name in btor witness file | Miodrag Milanovic | 2022-03-11 | 1 | -5/+14 | |
| * | | | Proper write of memory data | Miodrag Milanovic | 2022-03-11 | 1 | -14/+13 | |
| * | | | Start work on memory init | Miodrag Milanovic | 2022-03-09 | 1 | -9/+34 | |
| * | | | Fixes and error check | Miodrag Milanovic | 2022-03-09 | 1 | -1/+5 | |
| * | | | cleanup | Miodrag Milanovic | 2022-03-07 | 1 | -1/+2 | |
| * | | | Error checks for aiger witness | Miodrag Milanovic | 2022-03-07 | 1 | -0/+7 | |
| * | | | btor2 witness co-simulation | Miodrag Milanovic | 2022-03-07 | 1 | -8/+123 | |
| * | | | Merge pull request #3219 from YosysHQ/micko/quick_vcd | Miodrag Milanović | 2022-03-04 | 1 | -0/+1 | |
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| | * | | | VCD reader support by using external tool | Miodrag Milanovic | 2022-02-28 | 1 | -0/+1 | |
| * | | | | Add option to ignore X only signals in output | Miodrag Milanovic | 2022-03-02 | 1 | -8/+32 | |
| * | | | | Write simulation files after simulation is performed | Miodrag Milanovic | 2022-03-02 | 1 | -145/+151 | |
| * | | | | Cleanup | Miodrag Milanovic | 2022-03-02 | 1 | -10/+7 | |
| * | | | | Refactor sim output writers | Miodrag Milanovic | 2022-02-28 | 1 | -213/+257 | |
| * | | | | Quick fix | Miodrag Milanovic | 2022-02-28 | 1 | -0/+2 | |
| * | | | | Add writing of aiw files to "sim" command | Claire Xenia Wolf | 2022-02-28 | 1 | -1/+87 | |
| * | | | | Hotfix in AIGER witness reader state machine | Claire Xenia Wolf | 2022-02-28 | 1 | -0/+1 | |
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| * | | | Support extended aiw format | Miodrag Milanovic | 2022-02-27 | 1 | -23/+44 | |
| * | | | Fix for last clock edge data | Miodrag Milanovic | 2022-02-25 | 1 | -3/+1 | |
| * | | | Experimental sim changes | Claire Xenia Wolf | 2022-02-25 | 1 | -20/+22 | |
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