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* opt_lut: leave intact LUTs with cascade feeding module outputs.whitequark2018-12-071-0/+6
* opt_lut: show original truth table for both cells.whitequark2018-12-071-2/+3
* opt_lut: add -limit option, for debugging misoptimizations.whitequark2018-12-071-3/+21
* Bugfix in opt_expr handling of a<0 and a>=0Clifford Wolf2018-12-061-1/+1
* Rename opt_lut.cpp to opt_lut.ccClifford Wolf2018-12-051-0/+0
* opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.whitequark2018-12-051-17/+163
* opt_lut: always prefer to eliminate 1-LUTs.whitequark2018-12-051-19/+41
* opt_lut: collect and display statistics.whitequark2018-12-051-4/+33
* opt_lut: refactor to use a worker. NFC.whitequark2018-12-051-170/+177
* opt_lut: new pass, to combine LUTs for tighter packing.whitequark2018-12-052-0/+275
* Fix typoClifford Wolf2018-12-041-1/+1
* Merge pull request #702 from smunaut/min_ce_useClifford Wolf2018-12-041-1/+36
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| * dff2dffe: Add option for unmap to only remove DFFE with low CE signal useSylvain Munaut2018-11-271-1/+36
* | Merge pull request #676 from rafaeltp/masterClifford Wolf2018-12-011-10/+17
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| * using [i] to access individual bits of SigSpec and merging bits into a tmp Si...rafaeltp2018-10-211-11/+12
| * cleaning up for PRrafaeltp2018-10-201-2/+2
| * fixing code stylerafaeltp2018-10-201-1/+1
| * solves #675rafaeltp2018-10-201-11/+17
* | Add iteration limit to "opt_muxtree"Clifford Wolf2018-11-201-1/+17
* | DFFLIBMAP: changed 'missing pin' error into a warning with additional reason/...Niels Moseley2018-11-061-1/+10
* | Allow square brackets in liberty identifiersClifford Wolf2018-11-051-2/+2
* | Liberty file newline handling is more relaxed. More descriptive error messageNiels Moseley2018-11-031-4/+7
* | Report an error when a liberty file contains pin references that reference no...Niels Moseley2018-11-031-0/+3
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* Refactor code to avoid code duplication + added commentsRuben Undheim2018-10-201-2/+5
* Support for SystemVerilog interfaces as a port in the top level module + test...Ruben Undheim2018-10-201-5/+36
* Merge pull request #672 from daveshah1/fix_bramClifford Wolf2018-10-191-0/+1
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| * memory_bram: Reset make_outreg when growing read portsDavid Shah2018-10-191-0/+1
* | Merge pull request #659 from rubund/sv_interfacesClifford Wolf2018-10-181-7/+188
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| * | Documentation improvements etc.Ruben Undheim2018-10-131-27/+38
| * | Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-1/+13
| * | Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-7/+165
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* | stop check_signal_in_fanout from traversing FFstklam2018-10-131-2/+2
* | stop check_signal_in_fanout from traversing FFstklam2018-10-131-1/+12
* | fix bug: pass by referencetklam2018-09-261-1/+1
* | Fix issue #639TK Lam2018-09-261-0/+58
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* Merge pull request #625 from aman-goel/masterClifford Wolf2018-09-141-1/+7
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| * Minor revision to -expose in setundef passAman Goel2018-09-101-1/+7
* | Fixed minor typo in "sim" help messageacw12512018-09-121-1/+1
* | Merge pull request #606 from cr1901/show-winClifford Wolf2018-08-191-3/+20
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| * Update show pass documentation with Windows caveats.William D. Jones2018-08-151-1/+2
| * Fix run_command() when using -format and -viewer in show pass.William D. Jones2018-08-151-2/+18
* | Revision to expose option in setundef passAman Goel2018-08-181-154/+123
* | Merge pull request #3 from YosysHQ/masterAman Goel2018-08-18121-263/+411
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| * Merge pull request #591 from hzeller/virtual-overrideClifford Wolf2018-08-15120-265/+264
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| | * Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-20120-265/+264
| * | Add missing <deque> include (MSVC build fix)Clifford Wolf2018-07-221-0/+1
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| * Add async2sync passClifford Wolf2018-07-192-0/+148
* | Merge pull request #2 from YosysHQ/masterAman Goel2018-07-183-3/+155
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| * ecp5: Adding synchronous set/reset supportDavid Shah2018-07-143-3/+155
* | Merging with official repoAman Goel2018-07-048-65/+236
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