iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Minor bugfix in FSM reset state detection	Clifford Wolf	2016-07-12	1	-2/+5
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*	Further improved fsm_detect output, attempt to detect self-resetting circuits	Clifford Wolf	2016-07-09	1	-6/+68
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*	Added printing of some warning messages to fsm_detect	Clifford Wolf	2016-07-09	1	-14/+61
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*	Replaced "select -assert-limit" with -assert-max and -assert-min	Clifford Wolf	2016-07-01	1	-42/+29
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*	Added 'assert-limit' option for 'select' command	eshellko	2016-07-01	1	-5/+42
\| \| \|	For resource limited designs such as FPGA it can be useful to specify limit of specific resources available on board. So user can check if he should change RTL as early as mapping done.
*	Bugfix in "abc -script" handling	Clifford Wolf	2016-06-19	1	-53/+50
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*	Added "deminout"	Clifford Wolf	2016-06-19	2	-0/+117
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*	Added "dc2" to default ABC scripts	Clifford Wolf	2016-06-17	1	-5/+5
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*	Added "abc -I <num> -P <num>"	Clifford Wolf	2016-06-17	1	-8/+33
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*	Improved support for $sop cells	Clifford Wolf	2016-06-17	2	-2/+69
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*	Added $sop cell type and "abc -sop"	Clifford Wolf	2016-06-17	1	-6/+23
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*	Updated ABC to hg rev b5df6e2b76f0	Clifford Wolf	2016-06-17	1	-9/+9
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*	Added "nlutmap -assert"	Clifford Wolf	2016-06-09	1	-0/+14
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*	Added "proc_mux -ifx"	Clifford Wolf	2016-06-06	2	-19/+43
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*	Added "setundef -init"	Clifford Wolf	2016-06-03	1	-5/+89
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*	Fix all undef-muxes in dlatch input cone	Clifford Wolf	2016-06-02	1	-34/+72
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*	Avoid creating undef-muxes when inferring latches in proc_dlatch	Clifford Wolf	2016-06-01	1	-0/+44
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*	Added opt_expr support for div/mod by power-of-two	Clifford Wolf	2016-05-29	1	-0/+69
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*	Fixed "scc" for cells that have feedback singals _and_ are part of a larger loop	Clifford Wolf	2016-05-27	1	-3/+3
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*	Made the expansion order of hierarchy deterministic	Marcus Comstedt	2016-05-22	1	-3/+3
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*	Improvements and fixes in autotest.sh script and test_autotb	Clifford Wolf	2016-05-20	1	-3/+3
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*	Close opened dump file.	Kaj Tuomi	2016-05-19	1	-0/+1
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*	Fix for Modelsim transcript line warp issue #164	Kaj Tuomi	2016-05-19	1	-7/+13
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*	Don't sign-extend memory bram initialization data	Clifford Wolf	2016-05-15	1	-1/+1
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*	Added support for "keep" attribute to shregmap	Clifford Wolf	2016-05-07	1	-2/+2
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*	Fixed preservation of important attributes in techmap	Clifford Wolf	2016-05-06	1	-4/+32
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*	Changed port names in greenpak shregmap	Andrew Zonenberg	2016-05-04	1	-1/+1
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*	Added tristate buffer support to iopadmap	Clifford Wolf	2016-05-04	1	-4/+161
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*	Fixed iopadmap attribute handling	Clifford Wolf	2016-05-04	1	-0/+1
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*	Added "qwp -v"	Clifford Wolf	2016-04-28	1	-0/+30
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*	Connections between inputs and inouts are driven by the input	Clifford Wolf	2016-04-26	1	-0/+3
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*	Fixed test_autotb for modules with many cell ports	Clifford Wolf	2016-04-25	1	-3/+6
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*	Fixed proc_mux performance bug	Clifford Wolf	2016-04-25	1	-0/+3
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*	Fixed performance bug in proc_dlatch	Clifford Wolf	2016-04-24	1	-2/+61
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*	Improvements in greenpak4 shreg mapping	Clifford Wolf	2016-04-23	1	-16/+35
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*	Merge https://github.com/cliffordwolf/yosys	Andrew Zonenberg	2016-04-23	1	-0/+1
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\| *	Added "shregmap -zinit" for greenpak4 tech	Clifford Wolf	2016-04-23	1	-0/+1
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* \|	Fixed typo in help text	Andrew Zonenberg	2016-04-22	1	-1/+1
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*	Added "shregmap -tech greenpak4"	Clifford Wolf	2016-04-22	1	-6/+97
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*	More flexible handling of initialization values	Clifford Wolf	2016-04-22	1	-7/+22
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*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	80	-102/+102
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*	Fixed performance bug in "share" pass	Clifford Wolf	2016-04-21	1	-2/+51
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*	Improvements in opt_expr	Clifford Wolf	2016-04-21	1	-12/+62
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*	Bugfix and improvements in memory_share	Clifford Wolf	2016-04-21	1	-22/+19
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*	Added "shregmap -params"	Clifford Wolf	2016-04-18	1	-4/+43
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*	Added "shregmap -zinit" and "shregmap -init"	Clifford Wolf	2016-04-18	1	-2/+65
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*	Improvements in "shregmap"	Clifford Wolf	2016-04-17	1	-30/+140
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*	Added "shregmap" pass	Clifford Wolf	2016-04-16	2	-0/+262
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*	Fixed copy&paste error in log message in lut2mux	Clifford Wolf	2016-04-16	1	-1/+1
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*	Prefer noninverting FFs in dfflibmap	Clifford Wolf	2016-04-05	1	-4/+20
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