| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | | | Add copyright | Eddie Hung | 2019-08-22 | 1 | -0/+1 | |
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| | * | | | | Remove `shregmap -tech xilinx` additions | Eddie Hung | 2019-08-22 | 1 | -189/+8 | |
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| | * | | | | pmgen to also iterate over all module ports | Eddie Hung | 2019-08-22 | 1 | -2/+4 | |
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| | * | | | | Remove output_bits | Eddie Hung | 2019-08-22 | 2 | -16/+7 | |
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| | * | | | | Forgot to set ud_variable.minlen | Eddie Hung | 2019-08-22 | 1 | -0/+1 | |
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| | * | | | | Do not run xilinx_srl_pm in fixed loop | Eddie Hung | 2019-08-22 | 1 | -28/+24 | |
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| | * | | | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-22 | 1 | -7/+12 | |
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| | * \ \ \ \ | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-22 | 1 | -1/+1 | |
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| | * | | | | | | Reuse var | Eddie Hung | 2019-08-21 | 1 | -1/+1 | |
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| | * | | | | | | Revert "Trim shiftx_width when upper bits are 1'bx" | Eddie Hung | 2019-08-21 | 1 | -6/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 7e7965ca7b3bbeb79cb70014da7bc48c08a74adb. | |||||
| | * | | | | | | opt_expr to trim A port of $shiftx if Y_WIDTH == 1 | Eddie Hung | 2019-08-21 | 1 | -0/+17 | |
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| | * | | | | | | Trim shiftx_width when upper bits are 1'bx | Eddie Hung | 2019-08-21 | 1 | -1/+6 | |
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| | * | | | | | | Add comment | Eddie Hung | 2019-08-21 | 1 | -0/+4 | |
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| | * | | | | | | Add variable length support to xilinx_srl | Eddie Hung | 2019-08-21 | 2 | -14/+164 | |
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| | * | | | | | | Rename pattern to fixed | Eddie Hung | 2019-08-21 | 2 | -10/+10 | |
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| | * | | | | | | attribute -> attr | Eddie Hung | 2019-08-21 | 1 | -4/+4 | |
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| | * | | | | | | Use Cell::has_keep_attribute() | Eddie Hung | 2019-08-21 | 1 | -4/+4 | |
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| | * | | | | | | xilinx_srl to support FDRE and FDRE_1 | Eddie Hung | 2019-08-21 | 2 | -10/+73 | |
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| | * | | | | | | Fix polarity of EN_POL | Eddie Hung | 2019-08-21 | 1 | -2/+2 | |
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| | * | | | | | | Add CLKPOL == 0 | Eddie Hung | 2019-08-21 | 1 | -0/+2 | |
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| | * | | | | | | Reject if not minlen from inside pattern matcher | Eddie Hung | 2019-08-21 | 2 | -8/+11 | |
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| | * | | | | | | Get wire via SigBit | Eddie Hung | 2019-08-21 | 1 | -4/+4 | |
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| | * | | | | | | Respect \keep on cells or wires | Eddie Hung | 2019-08-21 | 1 | -2/+10 | |
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| | * | | | | | | Add init support | Eddie Hung | 2019-08-21 | 1 | -2/+11 | |
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| | * | | | | | | Fix spacing | Eddie Hung | 2019-08-21 | 1 | -2/+2 | |
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| | * | | | | | | Initial progress on xilinx_srl | Eddie Hung | 2019-08-21 | 3 | -0/+213 | |
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| * | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-28 | 10 | -122/+772 | |
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| | * \ \ \ \ \ \ | Merge pull request #1334 from YosysHQ/clifford/async2synclatch | Eddie Hung | 2019-08-28 | 1 | -1/+36 | |
| | |\ \ \ \ \ \ \ | | |_|_|_|_|_|/ | |/| | | | | | | Add $dlatch support to async2sync | |||||
| | | * | | | | | | Add $dlatch support to async2sync | Clifford Wolf | 2019-08-28 | 1 | -1/+36 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | | | Fix typo | Clifford Wolf | 2019-08-28 | 1 | -2/+2 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | | | Add "paramap" pass | Clifford Wolf | 2019-08-28 | 1 | -67/+118 | |
| | |/ / / / / / | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | | Merge pull request #1325 from YosysHQ/eddie/sat_init | Clifford Wolf | 2019-08-28 | 1 | -1/+1 | |
| | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | In sat: 'x' in init attr should be ignored | |||||
| | | * | | | | | | Ignore all 1'bx in (* init *) | Eddie Hung | 2019-08-27 | 1 | -3/+1 | |
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| | | * | | | | | | In sat: 'x' in init attr should not override constant | Eddie Hung | 2019-08-22 | 1 | -0/+2 | |
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| | * | | | | | | improve clkbuf_inhibit propagation upwards through hierarchy | Marcin Kościelnicki | 2019-08-27 | 1 | -1/+12 | |
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| | * | | | | | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-26 | 4 | -32/+279 | |
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| | | * | | | | | | indo -> into | Eddie Hung | 2019-08-23 | 1 | -1/+1 | |
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| | | * | | | | | Fix port hanlding in pmgen | Clifford Wolf | 2019-08-23 | 1 | -4/+3 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | | | | Add pmgen slices and choices | Clifford Wolf | 2019-08-23 | 4 | -28/+276 | |
| | | |/ / / / | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | clkbufmap to only check clkbuf_inhibit if no selection given | Eddie Hung | 2019-08-23 | 1 | -5/+18 | |
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| | * | | | | | Review comment from @cliffordwolf | Eddie Hung | 2019-08-23 | 1 | -1/+2 | |
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| | * | | | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 48 | -768/+2262 | |
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| | * | | | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-16 | 41 | -2157/+2152 | |
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| | * | | | | | | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 2 | -28/+9 | |
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| | * | | | | | | review fixes | Marcin Kościelnicki | 2019-08-13 | 2 | -29/+4 | |
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| | * | | | | | | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 3 | -20/+356 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it. | |||||
| * | | | | | | | Cleanup | Eddie Hung | 2019-08-23 | 1 | -130/+59 | |
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| * | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-23 | 3 | -7/+29 | |
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| | * | | | | | | Spelling | Eddie Hung | 2019-08-22 | 1 | -2/+2 | |
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| | * | | | | | Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx | Eddie Hung | 2019-08-22 | 1 | -4/+26 | |
| | |\ \ \ \ \ | | |_|_|_|/ | |/| | | | | opt_expr to trim A port of $shiftx/$shift | |||||
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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