iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Added module->ports	Clifford Wolf	2014-08-14	4	-8/+8
*	RIP $safe_pmux	Clifford Wolf	2014-08-14	8	-9/+7
*	Some improvements in FSM mapping and recoding	Clifford Wolf	2014-08-14	2	-8/+16
*	Added "abc -D" for setting delay target	Clifford Wolf	2014-08-14	1	-5/+18
*	Filter ANSI escape sequences from ABC output	Clifford Wolf	2014-08-13	1	-0/+15
*	Fixed handling of constant-true branches in proc_clean	Clifford Wolf	2014-08-12	2	-2/+3
*	Fixed FSM mapping for multiple reset-like signals	Clifford Wolf	2014-08-10	1	-1/+21
*	Fixed "share" for complex scenarios with never-active cells	Clifford Wolf	2014-08-09	1	-6/+22
*	Do not share any $reduce_* cells (its complicated and not worth it anyways)	Clifford Wolf	2014-08-09	1	-19/+0
*	Some improvements in fsm_opt and fsm_map for FSM with unreachable states	Clifford Wolf	2014-08-09	2	-50/+101
*	Another fsm_extract bugfix	Clifford Wolf	2014-08-08	1	-0/+4
*	Fixed "fsm -export"	Clifford Wolf	2014-08-08	2	-6/+5
*	Fixed sharing of reduce operator	Clifford Wolf	2014-08-08	1	-0/+13
*	Fixed fsm_extract for wreduced muxes	Clifford Wolf	2014-08-08	1	-8/+25
*	Added "sat -prove-skip"	Clifford Wolf	2014-08-08	1	-2/+16
*	Fixed build with gcc-4.6	Clifford Wolf	2014-08-07	1	-6/+6
*	Use "-keepdc" in "miter -equiv -flatten"	Clifford Wolf	2014-08-07	1	-2/+2
*	Various improvements in memory_dff pass	Clifford Wolf	2014-08-06	1	-21/+22
*	Various fixes and improvements in wreduce pass	Clifford Wolf	2014-08-05	1	-29/+47
*	Removed old "constmap" from wreduce code	Clifford Wolf	2014-08-05	1	-3/+2
*	Added support for truncating of wires to wreduce pass	Clifford Wolf	2014-08-05	1	-4/+40
*	Cleanups and improvements in wreduce pass	Clifford Wolf	2014-08-05	1	-47/+77
*	Added mux support to wreduce command	Clifford Wolf	2014-08-05	1	-36/+82
*	Added "show -signed"	Clifford Wolf	2014-08-04	1	-5/+17
*	Added RTLIL::IdString::in(...)	Clifford Wolf	2014-08-04	1	-4/+3
*	Fixed "share" for memory read ports	Clifford Wolf	2014-08-03	1	-0/+7
*	Progress in "wreduce" pass	Clifford Wolf	2014-08-03	1	-43/+16
*	Added "wreduce" command (work in progress)	Clifford Wolf	2014-08-03	2	-0/+253
*	Implemented recursive techmap	Clifford Wolf	2014-08-03	1	-16/+62
*	Fixes in show command (related to new IdString)	Clifford Wolf	2014-08-03	1	-20/+18
*	Implemented simplemap support for "techmap -extern"	Clifford Wolf	2014-08-02	1	-5/+40
*	Bugfix in "techmap -extern"	Clifford Wolf	2014-08-02	1	-0/+1
*	Removed at() method from RTLIL::IdString	Clifford Wolf	2014-08-02	1	-1/+1
*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	8	-10/+10
*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02	5	-11/+13
*	Fixed a performance bug in opt_reduce	Clifford Wolf	2014-08-02	1	-2/+6
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	26	-173/+176
*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02	4	-7/+7
*	Replaced sha1 implementation	Clifford Wolf	2014-08-01	3	-13/+2
*	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01	2	-6/+5
*	Added "test_autotb -n <num_iter>" option	Clifford Wolf	2014-08-01	1	-9/+27
*	Renamed modwalker.h to modtools.h	Clifford Wolf	2014-07-31	2	-10/+12
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	35	-709/+709
*	Added "trace" command	Clifford Wolf	2014-07-31	3	-2/+100
*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31	7	-9/+11
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	11	-15/+19
*	Renamed "stdcells.v" to "techmap.v"	Clifford Wolf	2014-07-31	3	-6/+6
*	Added "techmap -assert"	Clifford Wolf	2014-07-31	2	-14/+43
*	Added techmap CONSTMAP feature	Clifford Wolf	2014-07-30	1	-10/+119
*	Added write_file command	Clifford Wolf	2014-07-30	2	-0/+77