More bugfixes related to new RTLIL::IdString

5 files changed, 13 insertions, 11 deletions

diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index 35ca2f474..b4f4d26ae 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -490,7 +490,7 @@ static void select_op_expand(RTLIL::Design *design, std::string arg, char mode)
 						for (auto i2 : i1.second)
 							limits.insert(i2);
 					} else
-						log_cmd_error("Selection %s is not defined!\n", RTLIL::id2cstr(str));
+						log_cmd_error("Selection %s is not defined!\n", RTLIL::unescape_id(str).c_str());
 				} else
 					limits.insert(RTLIL::escape_id(str));
 			}
@@ -654,7 +654,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
 		if (design->selection_vars.count(set_name) > 0)
 			work_stack.push_back(design->selection_vars[set_name]);
 		else
-			log_cmd_error("Selection @%s is not defined!\n", RTLIL::id2cstr(set_name));
+			log_cmd_error("Selection @%s is not defined!\n", RTLIL::unescape_id(set_name).c_str());
 		select_filter_active_mod(design, work_stack.back());
 		return;
 	}
@@ -1315,7 +1315,7 @@ struct CdPass : public Pass {
 			return;
 		}
 
-		log_cmd_error("No such module `%s' found!\n", RTLIL::id2cstr(modname));
+		log_cmd_error("No such module `%s' found!\n", RTLIL::unescape_id(modname).c_str());
 	}
 } CdPass;
 
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 28b4ad990..50b4989df 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -28,7 +28,7 @@
 namespace {
 	struct generate_port_decl_t {
 		bool input, output;
-		std::string portname;
+		RTLIL::IdString portname;
 		int index;
 	};
 }
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc
index 1475b855e..e51c92f9f 100644
--- a/passes/sat/miter.cc
+++ b/passes/sat/miter.cc
@@ -59,9 +59,9 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 	if (argidx+3 != args.size() || args[argidx].substr(0, 1) == "-")
 		that->cmd_error(args, argidx, "command argument error");
 	
-	std::string gold_name = RTLIL::escape_id(args[argidx++]);
-	std::string gate_name = RTLIL::escape_id(args[argidx++]);
-	std::string miter_name = RTLIL::escape_id(args[argidx++]);
+	RTLIL::IdString gold_name = RTLIL::escape_id(args[argidx++]);
+	RTLIL::IdString gate_name = RTLIL::escape_id(args[argidx++]);
+	RTLIL::IdString miter_name = RTLIL::escape_id(args[argidx++]);
 
 	if (design->modules_.count(gold_name) == 0)
 		log_cmd_error("Can't find gold module %s!\n", gold_name.c_str());
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 6ebac265c..06af2923b 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -700,7 +700,7 @@ struct ExtractPass : public Pass {
 				log("\nFrequent SubCircuit with %d nodes and %d matches:\n", int(result.nodes.size()), result.totalMatchesAfterLimits);
 				log("  primary match in %s:", id2cstr(haystack_map.at(result.graphId)->name));
 				for (auto &node : result.nodes)
-					log(" %s", id2cstr(node.nodeId));
+					log(" %s", RTLIL::unescape_id(node.nodeId).c_str());
 				log("\n");
 				for (auto &it : result.matchesPerGraph)
 					log("  matches in %s: %d\n", id2cstr(haystack_map.at(it.first)->name), it.second);
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 2bcd3003e..374fa9bf2 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -57,7 +57,7 @@ struct TechmapWorker
 	std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
 	std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
 	std::map<RTLIL::Module*, bool> techmap_do_cache;
-	std::set<RTLIL::Module*> module_queue;
+	std::set<RTLIL::Module*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Module>> module_queue;
 
 	struct TechmapWireData {
 		RTLIL::Wire *wire;
@@ -479,7 +479,7 @@ struct TechmapWorker
 								cmd_string = cmd_string.substr(strlen("CONSTMAP; "));
 
 								log("Analyzing pattern of constant bits for this cell:\n");
-								std::string new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true);
+								RTLIL::IdString new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true);
 								log("Creating constmapped module `%s'.\n", log_id(new_tpl_name));
 								log_assert(map->module(new_tpl_name) == nullptr);
 
@@ -824,7 +824,9 @@ struct TechmapPass : public Pass {
 				celltypeMap[it.first].insert(it.first);
 		}
 
-		worker.module_queue = design->modules();
+		for (auto module : design->modules())
+			worker.module_queue.insert(module);
+
 		while (!worker.module_queue.empty())
 		{
 			RTLIL::Module *module = *worker.module_queue.begin();