| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
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| | | * | | Updating initial state and checks | Miodrag Milanovic | 2022-01-31 | 1 | -15/+28 | |
| | | * | | Fix scope | Miodrag Milanovic | 2022-01-31 | 1 | -1/+1 | |
| | | * | | check if stop before start | Miodrag Milanovic | 2022-01-28 | 1 | -0/+3 | |
| | | * | | set initial state, only flip-flops | Miodrag Milanovic | 2022-01-28 | 1 | -1/+28 | |
| | | * | | ignore not found private signals | Miodrag Milanovic | 2022-01-28 | 1 | -0/+3 | |
| | | * | | recursive check | Miodrag Milanovic | 2022-01-28 | 1 | -26/+34 | |
| | | * | | Do actual compare | Miodrag Milanovic | 2022-01-28 | 1 | -5/+16 | |
| | | * | | Add more options and time handling | Miodrag Milanovic | 2022-01-28 | 1 | -2/+103 | |
| | | * | | Display values of outputs | Miodrag Milanovic | 2022-01-26 | 1 | -12/+10 | |
| | | * | | Check if stimulated | Miodrag Milanovic | 2022-01-26 | 1 | -0/+14 | |
| | | * | | Read fst and use data to set inputs | Miodrag Milanovic | 2022-01-26 | 1 | -10/+92 | |
| | | * | | Add ability to write to FST file | Miodrag Milanovic | 2022-01-26 | 1 | -11/+109 | |
| | * | | | Correct a typo in the manual | YRabbit | 2022-02-02 | 1 | -1/+1 | |
| | * | | | Update comment | Scott Thibault | 2022-02-02 | 1 | -1/+1 | |
| | * | | | Fix unextend method for signed constants | Scott Thibault | 2022-02-02 | 1 | -2/+1 | |
| | * | | | opt_reduce: Add $bmux and $demux optimization patterns. | Marcelina Kościelnicka | 2022-01-30 | 1 | -60/+337 | |
| | * | | | Add $bmux and $demux cells. | Marcelina Kościelnicka | 2022-01-28 | 8 | -3/+239 | |
| | * | | | opt_dff: Don't mutate muxes while ModWalker is active. | Marcelina Kościelnicka | 2022-01-28 | 1 | -98/+112 | |
| | * | | | memory_bram: Make use of new mem emulation functions to map more RAMs. | Marcelina Kościelnicka | 2022-01-27 | 1 | -18/+10 | |
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| | * | | opt_dff: fix sequence point copy paste bug | Austin Seipp | 2022-01-04 | 1 | -1/+1 | |
| | * | | memory_share: Fix SAT-based sharing for wide ports. | Marcelina Kościelnicka | 2021-12-20 | 1 | -1/+3 | |
| | * | | bugpoint: avoid infinite loop between -connections and -wires. | Catherine | 2021-12-15 | 1 | -1/+1 | |
| | * | | Add clean_zerowidth pass, use it for Verilog output. | Marcelina Kościelnicka | 2021-12-12 | 2 | -1/+212 | |
| | * | | opt_mem_priority: Fix non-ascii char in help message. | Marcelina Kościelnicka | 2021-12-09 | 1 | -1/+1 | |
| | * | | sta: very crude static timing analysis pass | Lofty | 2021-11-25 | 3 | -30/+341 | |
| | * | | show: Fix wire bit indexing. | Marcelina Kościelnicka | 2021-11-12 | 1 | -3/+16 | |
| | * | | Merge pull request #3077 from YosysHQ/claire/genlib | Claire Xen | 2021-11-10 | 1 | -21/+40 | |
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| | | * | | Spelling fix in abc.cc | Claire Xen | 2021-11-10 | 1 | -1/+1 | |
| | | * | | Add genlib support to ABC command | Claire Xenia Wolf | 2021-11-10 | 1 | -21/+40 | |
| | * | | | iopadmap: Fix ebmarassing typo | Marcelina Kościelnicka | 2021-11-10 | 1 | -1/+1 | |
| | * | | | iopadmap: Add native support for negative-polarity output enable. | Marcelina Kościelnicka | 2021-11-09 | 1 | -7/+22 | |
| | * | | | gowin: widelut support (#3042) | Pepijn de Vos | 2021-11-06 | 1 | -2/+8 | |
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| | * | | Make it work on all | Miodrag Milanovic | 2021-11-05 | 1 | -2/+4 | |
| | * | | Correct way of setting maybe_unsused on labels | Miodrag Milanovic | 2021-11-05 | 1 | -4/+2 | |
| | * | | flatten: Keep sigmap around between flatten_cell invocations. | Marcelina Kościelnicka | 2021-11-02 | 1 | -3/+4 | |
| | * | | proc_dff: Emit $aldff. | Marcelina Kościelnicka | 2021-10-27 | 1 | -32/+7 | |
| | * | | dfflegalize: Refactor, add aldff support. | Marcelina Kościelnicka | 2021-10-27 | 1 | -973/+889 | |
| | * | | verilog: use derived module info to elaborate cell connections | Zachary Snow | 2021-10-25 | 2 | -1/+7 | |
| | * | | Split out logic for reprocessing an AstModule | Rupert Swarbrick | 2021-10-25 | 1 | -1/+1 | |
| | * | | Change implicit conversions from bool to Sig* to explicit. | Marcelina Kościelnicka | 2021-10-21 | 1 | -4/+6 | |
| | * | | extract_reduce: Refactor and fix input signal construction. | Marcelina Kościelnicka | 2021-10-21 | 1 | -63/+34 | |
| | * | | dfflegalize: remove redundant check for initialized dlatch | Paul Annesley | 2021-10-17 | 1 | -4/+0 | |
| | * | | FfData: some refactoring. | Marcelina Kościelnicka | 2021-10-07 | 7 | -87/+48 | |
| | * | | Hook up $aldff support in various passes. | Marcelina Kościelnicka | 2021-10-02 | 3 | -4/+16 | |
| | * | | zinit: Refactor to use FfData. | Marcelina Kościelnicka | 2021-10-02 | 1 | -101/+38 | |
| | * | | kernel/ff: Refactor FfData to enable FFs with async load. | Marcelina Kościelnicka | 2021-10-02 | 5 | -130/+220 | |
| | * | | simplemap: refactor to use FfData. | Marcelina Kościelnicka | 2021-10-02 | 2 | -287/+20 | |
| | * | | abc9: make re-entrant (#2993) | Eddie Hung | 2021-09-09 | 2 | -9/+9 | |
| | * | | abc9: holes module to instantiate cells with NEW_ID (#2992) | Eddie Hung | 2021-09-09 | 1 | -1/+1 | |
| | * | | abc9: replace cell type/parameters if derived type already processed (#2991) | Eddie Hung | 2021-09-09 | 1 | -6/+22 | |
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index : iCE40/yosys | |
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