iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Still loop bug in "share": changed assert to warning	Clifford Wolf	2014-09-21	1	-13/+25
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*	Do not introduce new logic loops in "share"	Clifford Wolf	2014-09-21	1	-6/+47
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*	Assert on new logic loops in "share" pass	Clifford Wolf	2014-09-21	1	-0/+48
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*	Added "test_abcloop" command	Clifford Wolf	2014-09-19	2	-0/+286
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*	Small improvements in "abc" command handle_loops() function	Clifford Wolf	2014-09-19	1	-6/+9
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*	Using "NOT" instead of "INV" as cell name in default abc genlib file	Clifford Wolf	2014-09-19	1	-2/+2
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*	Alphabetically sort port names in "show" output	Clifford Wolf	2014-09-19	1	-0/+3
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*	Do not run "scorr" in "abc -fast"	Clifford Wolf	2014-09-18	1	-4/+4
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*	Added "abc -fast"	Clifford Wolf	2014-09-18	1	-6/+31
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*	Fixed $_NOR vs. $_NOR_ typo in abc.cc	Clifford Wolf	2014-09-16	1	-1/+1
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*	Fixed $memwr/$memrd order in memory_dff	Clifford Wolf	2014-09-16	1	-4/+6
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*	More aggressive $macc merging in alumacc	Clifford Wolf	2014-09-15	1	-1/+37
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*	Added the obvious optimizations to alumacc $macc generator	Clifford Wolf	2014-09-15	1	-0/+1
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*	Improved maccmap tree bit packing	Clifford Wolf	2014-09-15	1	-16/+50
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*	Fixed wreduce $shiftx handling	Clifford Wolf	2014-09-15	1	-1/+1
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*	Fixed techmap_wrap for techmap_celltype	Clifford Wolf	2014-09-14	1	-9/+16
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*	Various fixes/cleanups in alumacc and maccmap	Clifford Wolf	2014-09-14	2	-2/+11
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*	Added techmap_wrap attribute	Clifford Wolf	2014-09-14	1	-5/+28
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*	alumacc fix for $pos cells	Clifford Wolf	2014-09-14	1	-13/+24
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*	Extract $alu cells in alumacc	Clifford Wolf	2014-09-14	1	-1/+296
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*	Merge $macc cells in alumacc pass	Clifford Wolf	2014-09-14	1	-1/+59
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*	Basic $macc extract in alumacc	Clifford Wolf	2014-09-14	1	-4/+104
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*	alumacc skeleton	Clifford Wolf	2014-09-14	2	-0/+64
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*	Cleanup in wreduce	Clifford Wolf	2014-09-14	1	-11/+8
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*	Added $lcu cell type	Clifford Wolf	2014-09-08	1	-1/+26
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*	Added "$fa" cell type	Clifford Wolf	2014-09-08	2	-6/+47
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*	Trim msb/lsb zero bits from full adder in maccmap	Clifford Wolf	2014-09-08	1	-5/+27
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*	Added "test_cell -const"	Clifford Wolf	2014-09-08	1	-2/+45
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*	Added 'techmap_maccmap' techmap attribute	Clifford Wolf	2014-09-07	1	-19/+53
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*	Added "maccmap" command	Clifford Wolf	2014-09-07	2	-0/+319
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*	Added "test_cell -nosat"	Clifford Wolf	2014-09-07	1	-59/+73
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*	Various bug fixes (related to $macc model testing)	Clifford Wolf	2014-09-06	1	-1/+1
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*	Added $macc SAT model	Clifford Wolf	2014-09-06	1	-5/+6
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*	Added $macc cell type	Clifford Wolf	2014-09-06	1	-2/+53
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2014-09-06	9	-15/+15
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\| *	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06	9	-15/+15
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* \|	Added "test_cell -script"	Clifford Wolf	2014-09-06	1	-1/+8
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*	Fixed "opt_const -fine" for $pos cells	Clifford Wolf	2014-09-04	1	-9/+4
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*	Removed $bu0 cell type	Clifford Wolf	2014-09-04	6	-24/+9
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*	Fixed "test_cells -vlog"	Clifford Wolf	2014-09-03	1	-4/+6
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*	Improvements in "test_cell -vlog"	Clifford Wolf	2014-09-02	1	-3/+8
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*	Added test_cell -vlog	Clifford Wolf	2014-09-02	1	-2/+79
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*	Added SAT testing to test_cell eval stage	Clifford Wolf	2014-09-02	1	-1/+89
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*	Removed references to yosys-svgviewer from docs	Clifford Wolf	2014-09-02	1	-2/+2
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*	Using "xdot" instead of "yosys-svgviewer" in show command	Clifford Wolf	2014-09-02	1	-4/+3
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*	Added $alu support to test_cell	Clifford Wolf	2014-09-01	1	-1/+22
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*	Added "test_cell -simlib -v"	Clifford Wolf	2014-09-01	1	-8/+29
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*	Added "techmap -autoproc"	Clifford Wolf	2014-09-01	1	-2/+18
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*	Fixes in old SAT example.ys	Clifford Wolf	2014-09-01	1	-3/+4
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*	Moved "share" and "wreduce" to passes/opt/	Clifford Wolf	2014-09-01	5	-2/+2
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