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* Still loop bug in "share": changed assert to warningClifford Wolf2014-09-211-13/+25
* Do not introduce new logic loops in "share"Clifford Wolf2014-09-211-6/+47
* Assert on new logic loops in "share" passClifford Wolf2014-09-211-0/+48
* Added "test_abcloop" commandClifford Wolf2014-09-192-0/+286
* Small improvements in "abc" command handle_loops() functionClifford Wolf2014-09-191-6/+9
* Using "NOT" instead of "INV" as cell name in default abc genlib fileClifford Wolf2014-09-191-2/+2
* Alphabetically sort port names in "show" outputClifford Wolf2014-09-191-0/+3
* Do not run "scorr" in "abc -fast"Clifford Wolf2014-09-181-4/+4
* Added "abc -fast"Clifford Wolf2014-09-181-6/+31
* Fixed $_NOR vs. $_NOR_ typo in abc.ccClifford Wolf2014-09-161-1/+1
* Fixed $memwr/$memrd order in memory_dffClifford Wolf2014-09-161-4/+6
* More aggressive $macc merging in alumaccClifford Wolf2014-09-151-1/+37
* Added the obvious optimizations to alumacc $macc generatorClifford Wolf2014-09-151-0/+1
* Improved maccmap tree bit packingClifford Wolf2014-09-151-16/+50
* Fixed wreduce $shiftx handlingClifford Wolf2014-09-151-1/+1
* Fixed techmap_wrap for techmap_celltypeClifford Wolf2014-09-141-9/+16
* Various fixes/cleanups in alumacc and maccmapClifford Wolf2014-09-142-2/+11
* Added techmap_wrap attributeClifford Wolf2014-09-141-5/+28
* alumacc fix for $pos cellsClifford Wolf2014-09-141-13/+24
* Extract $alu cells in alumaccClifford Wolf2014-09-141-1/+296
* Merge $macc cells in alumacc passClifford Wolf2014-09-141-1/+59
* Basic $macc extract in alumaccClifford Wolf2014-09-141-4/+104
* alumacc skeletonClifford Wolf2014-09-142-0/+64
* Cleanup in wreduceClifford Wolf2014-09-141-11/+8
* Added $lcu cell typeClifford Wolf2014-09-081-1/+26
* Added "$fa" cell typeClifford Wolf2014-09-082-6/+47
* Trim msb/lsb zero bits from full adder in maccmapClifford Wolf2014-09-081-5/+27
* Added "test_cell -const"Clifford Wolf2014-09-081-2/+45
* Added 'techmap_maccmap' techmap attributeClifford Wolf2014-09-071-19/+53
* Added "maccmap" commandClifford Wolf2014-09-072-0/+319
* Added "test_cell -nosat"Clifford Wolf2014-09-071-59/+73
* Various bug fixes (related to $macc model testing)Clifford Wolf2014-09-061-1/+1
* Added $macc SAT modelClifford Wolf2014-09-061-5/+6
* Added $macc cell typeClifford Wolf2014-09-061-2/+53
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-09-069-15/+15
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| * Corrected spelling mistakes found by lintianRuben Undheim2014-09-069-15/+15
* | Added "test_cell -script"Clifford Wolf2014-09-061-1/+8
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* Fixed "opt_const -fine" for $pos cellsClifford Wolf2014-09-041-9/+4
* Removed $bu0 cell typeClifford Wolf2014-09-046-24/+9
* Fixed "test_cells -vlog"Clifford Wolf2014-09-031-4/+6
* Improvements in "test_cell -vlog"Clifford Wolf2014-09-021-3/+8
* Added test_cell -vlogClifford Wolf2014-09-021-2/+79
* Added SAT testing to test_cell eval stageClifford Wolf2014-09-021-1/+89
* Removed references to yosys-svgviewer from docsClifford Wolf2014-09-021-2/+2
* Using "xdot" instead of "yosys-svgviewer" in show commandClifford Wolf2014-09-021-4/+3
* Added $alu support to test_cellClifford Wolf2014-09-011-1/+22
* Added "test_cell -simlib -v"Clifford Wolf2014-09-011-8/+29
* Added "techmap -autoproc"Clifford Wolf2014-09-011-2/+18
* Fixes in old SAT example.ysClifford Wolf2014-09-011-3/+4
* Moved "share" and "wreduce" to passes/opt/Clifford Wolf2014-09-015-2/+2
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