iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Cleanup	Eddie Hung	2019-06-17	1	-3/+3
*	Merge branch 'xaig' into xaig_dff	Eddie Hung	2019-06-17	1	-1/+1
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\| *	&scorr before &sweep, remove &retime as recommended	Eddie Hung	2019-06-17	1	-1/+1
* \|	Merge branch 'xaig' into xaig_dff	Eddie Hung	2019-06-17	1	-3/+4
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\| *	Copy not move parameters/attributes	Eddie Hung	2019-06-17	1	-3/+4
* \|	Merge branch 'xaig' into xaig_dff	Eddie Hung	2019-06-17	1	-23/+26
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\| *	Fix leak removing cells during ABC integration; also preserve attr	Eddie Hung	2019-06-17	1	-25/+26
* \|	Merge remote-tracking branch 'origin/xaig' into xaig_dff	Eddie Hung	2019-06-17	1	-1/+1
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\| *	Re-enable &dc2	Eddie Hung	2019-06-17	1	-1/+1
\| *	Cleanup	Eddie Hung	2019-06-16	1	-51/+7
* \|	Cleanup	Eddie Hung	2019-06-15	1	-40/+7
* \|	abc9 to recover_init by default	Eddie Hung	2019-06-15	1	-11/+6
* \|	Do not treat $__ABC_FF_ as a user cell	Eddie Hung	2019-06-15	1	-21/+6
* \|	Cleanup	Eddie Hung	2019-06-15	1	-10/+7
* \|	Use $__ABC_FF_ instead of $_FF_	Eddie Hung	2019-06-15	1	-13/+21
* \|	Fix initialisation of flops	Eddie Hung	2019-06-15	1	-2/+3
* \|	Map to $_FF_ instead of $_DFF_P_ to prevent recursion issues	Eddie Hung	2019-06-15	1	-13/+13
* \|	For now, short $_DFF_[NP]_ from ff_map.v at re-integration	Eddie Hung	2019-06-15	1	-0/+8
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*	Get rid of compiler warnings	Eddie Hung	2019-06-14	1	-5/+5
*	Update abc9 -D doc	Eddie Hung	2019-06-14	1	-1/+2
*	Enable "abc9 -D <num>" for timing-driven synthesis	Eddie Hung	2019-06-14	1	-9/+9
*	Further cleanup based on @daveshah1	Eddie Hung	2019-06-14	1	-10/+0
*	Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig	Eddie Hung	2019-06-14	1	-0/+9
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\| *	ecp5: Add abc9 option	David Shah	2019-06-14	1	-0/+9
* \|	Remove extra semicolon	Eddie Hung	2019-06-14	1	-1/+1
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*	Rip out all non FPGA stuff from abc9	Eddie Hung	2019-06-12	1	-343/+111
*	Fix spelling	Eddie Hung	2019-06-12	1	-1/+1
*	Revert "For 'stat' do not count modules with abc_box_id"	Eddie Hung	2019-06-12	1	-3/+0
*	Be more precise when connecting during ABC9 re-integration	Eddie Hung	2019-06-12	1	-1/+3
*	Remove hacky wideports_split from abc9	Eddie Hung	2019-06-12	1	-52/+4
*	Fix compile errors when #if 1 for debug	Eddie Hung	2019-06-12	1	-7/+8
*	Do not call abc9 if no outputs	Eddie Hung	2019-06-12	1	-54/+65
*	More write_xaiger cleanup	Eddie Hung	2019-06-12	1	-1/+1
*	Consistency	Eddie Hung	2019-06-12	1	-1/+1
*	Merge branch 'xc7mux' into xaig	Eddie Hung	2019-06-12	1	-1/+1
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\| *	Typo: wire delay is -W argument	Eddie Hung	2019-06-12	1	-1/+1
* \|	Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7...	Eddie Hung	2019-06-12	1	-6/+3
* \|	Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"	Eddie Hung	2019-06-12	2	-267/+0
* \|	Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"	Eddie Hung	2019-06-12	1	-14/+10
* \|	Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"	Eddie Hung	2019-06-12	1	-5/+13
* \|	Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"	Eddie Hung	2019-06-12	1	-13/+5
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*	Add "-W' wire delay arg to abc9, use from synth_xilinx	Eddie Hung	2019-06-11	1	-5/+13
*	Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7...	Eddie Hung	2019-06-11	1	-15/+10
*	Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux	Eddie Hung	2019-06-11	1	-10/+15
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\| *	Try way that doesn't involve creating a new wire	Eddie Hung	2019-06-11	1	-10/+15
* \|	Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux	Eddie Hung	2019-06-10	1	-3/+6
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\| *	If d_bit already in sigbit_chain_next, create extra wire	Eddie Hung	2019-06-10	1	-3/+6
\| *	Allow muxcover costs to be changed	Eddie Hung	2019-06-07	1	-12/+42
* \|	Revert "Rename shregmap -tech xilinx -> xilinx_dynamic"	Eddie Hung	2019-06-10	1	-4/+4
* \|	Revert "shregmap -tech xilinx_dynamic to work -params and -enpol"	Eddie Hung	2019-06-10	1	-26/+6