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author | Eddie Hung <eddie@fpgeh.com> | 2019-06-17 12:58:41 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-17 12:58:41 -0700 |
commit | 7dd3a7f161d57f8c1f4a26cc5645bbec1c9e687a (patch) | |
tree | 82324b5e68d132dd9c16e7b9ccde4211f1e1fa4f /passes | |
parent | 5ce672d1c502d24551e71a8296a672ff16411870 (diff) | |
parent | b45d06d7a334c4b18e44793b33aaffcaf1f04b21 (diff) | |
download | yosys-7dd3a7f161d57f8c1f4a26cc5645bbec1c9e687a.tar.gz yosys-7dd3a7f161d57f8c1f4a26cc5645bbec1c9e687a.tar.bz2 yosys-7dd3a7f161d57f8c1f4a26cc5645bbec1c9e687a.zip |
Merge branch 'xaig' into xaig_dff
Diffstat (limited to 'passes')
-rw-r--r-- | passes/techmap/abc9.cc | 49 |
1 files changed, 26 insertions, 23 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index e234ab28d..40c75159d 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -509,22 +509,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri } } - dict<IdString, decltype(RTLIL::Cell::parameters)> erased_boxes; - for (auto it = module->cells_.begin(); it != module->cells_.end(); ) { - RTLIL::Cell* cell = it->second; - if (cell->type.in("$_AND_", "$_NOT_", "$__ABC_FF_")) { - it = module->cells_.erase(it); - continue; - } - RTLIL::Module* box_module = design->module(cell->type); - if (box_module && box_module->attributes.count("\\abc_box_id")) { - erased_boxes.insert(std::make_pair(it->first, std::move(cell->parameters))); - it = module->cells_.erase(it); - continue; - } - ++it; - } - // Do the same for module connections for (auto &it : module->connections_) { auto &signal = it.first; auto bits = signal.bits(); @@ -534,6 +518,19 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri signal = std::move(bits); } + vector<RTLIL::Cell*> boxes; + for (auto it = module->cells_.begin(); it != module->cells_.end(); ) { + RTLIL::Cell* cell = it->second; + if (cell->type.in("$_AND_", "$_NOT_", "$__ABC_FF_")) { + it = module->remove(it); + continue; + } + RTLIL::Module* box_module = design->module(cell->type); + if (box_module && box_module->attributes.count("\\abc_box_id")) + boxes.emplace_back(it->second); + ++it; + } + std::map<std::string, int> cell_stats; for (auto c : mapped_mod->cells()) { @@ -602,18 +599,21 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri SigSpec my_a = module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]; SigSpec my_y = module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]; module->connect(my_y, my_a); + if (markgroups) c->attributes["\\abcgroup"] = map_autoidx; continue; } } - else { - auto it = erased_boxes.find(c->name); - log_assert(it != erased_boxes.end()); - c->parameters = std::move(it->second); - } - RTLIL::Cell* cell = module->addCell(remap_name(c->name), c->type); + RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type); if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; - cell->parameters = c->parameters; + RTLIL::Cell *existing_cell = module->cell(c->name); + if (existing_cell) { + cell->parameters = std::move(existing_cell->parameters); + cell->attributes = std::move(existing_cell->attributes); + } + else { + cell->parameters = std::move(c->parameters); + } for (auto &conn : c->connections()) { RTLIL::SigSpec newsig; for (auto c : conn.second.chunks()) { @@ -628,6 +628,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri } } + for (auto cell : boxes) + module->remove(cell); + // Copy connections (and rename) from mapped_mod to module for (auto conn : mapped_mod->connections()) { if (!conn.first.is_fully_const()) { |