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| | | * | | | | | | Revert "Try way that doesn't involve creating a new wire"Eddie Hung2019-06-111-15/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 2f427acc9ed23c77e89386f4fbf53ac580bf0f0b.
| | * | | | | | | | Merge pull request #1117 from bwidawsk/more-homeClifford Wolf2019-06-211-0/+4
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| | | * | | | | | | Add a few more filename rewritesBen Widawsky2019-06-201-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This now allows a full pipeline to work, something such as: yosys -p "synth_ecp5 -json ~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v" Otherwise, you will get something along the lines of: ERROR: Can't open output file `~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v' for writing: No such file or directory Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * | | | | | | | | Cope with $reduce_or common in caseEddie Hung2019-06-211-5/+37
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| * | | | | | | | | Fix spacingEddie Hung2019-06-211-24/+24
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| * | | | | | | | | Add docEddie Hung2019-06-211-3/+3
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| * | | | | | | | | Fix up ExclusiveDatabase with @cliffordwolf's helpEddie Hung2019-06-211-35/+34
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| * | | | | | | | | Merge branch 'master' into eddie/muxpackEddie Hung2019-06-218-11/+51
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| | * | | | | | | | Fix typo, fixes #1095Clifford Wolf2019-06-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | | | | | Improve shregmap help message, fixes #1113Clifford Wolf2019-06-201-0/+2
| | | |_|/ / / / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | | | | Fix typoClifford Wolf2019-06-201-2/+2
| | |/ / / / / / | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | | | Fixed the help summary line for a few commandsacw12512019-06-193-5/+5
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| | * | | | | | Fix bug in #1078, add entry to CHANGELOGEddie Hung2019-06-191-3/+3
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| | * | | | | | Use input default values in hierarchy passClifford Wolf2019-06-191-0/+38
| | | |_|/ / / | | |/| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | Elaborate muxpack docEddie Hung2019-06-101-2/+6
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| * | | | | | Merge remote-tracking branch 'origin/master' into eddie/muxpackEddie Hung2019-06-101-12/+42
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| * | | | | | Comment O(N) -> O(N^2)Eddie Hung2019-06-071-1/+1
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| * | | | | | Extend ExclusiveDatabase to query SigSpec-s (for $pmux)Eddie Hung2019-06-071-19/+27
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| * | | | | | Add ExclusiveDatabase to check exclusive $eq/$logic_not cell resultsEddie Hung2019-06-071-1/+64
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| * | | | | | Resolve @cliffordwolf comment on redundant checkEddie Hung2019-06-071-10/+2
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| * | | | | | Resolve @cliffordwolf comment on sigmapEddie Hung2019-06-071-2/+2
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* | | | | | | CleanupEddie Hung2019-06-171-3/+3
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* | | | | | | Merge branch 'xaig' into xaig_dffEddie Hung2019-06-171-1/+1
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| * | | | | | &scorr before &sweep, remove &retime as recommendedEddie Hung2019-06-171-1/+1
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* | | | | | | Merge branch 'xaig' into xaig_dffEddie Hung2019-06-171-3/+4
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| * | | | | | Copy not move parameters/attributesEddie Hung2019-06-171-3/+4
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* | | | | | | Merge branch 'xaig' into xaig_dffEddie Hung2019-06-171-23/+26
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| * | | | | | Fix leak removing cells during ABC integration; also preserve attrEddie Hung2019-06-171-25/+26
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* | | | | | | Merge remote-tracking branch 'origin/xaig' into xaig_dffEddie Hung2019-06-171-1/+1
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| * | | | | | Re-enable &dc2Eddie Hung2019-06-171-1/+1
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| * | | | | | CleanupEddie Hung2019-06-161-51/+7
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* | | | | | | CleanupEddie Hung2019-06-151-40/+7
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* | | | | | | abc9 to recover_init by defaultEddie Hung2019-06-151-11/+6
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* | | | | | | Do not treat $__ABC_FF_ as a user cellEddie Hung2019-06-151-21/+6
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* | | | | | | CleanupEddie Hung2019-06-151-10/+7
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* | | | | | | Use $__ABC_FF_ instead of $_FF_Eddie Hung2019-06-151-13/+21
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* | | | | | | Fix initialisation of flopsEddie Hung2019-06-151-2/+3
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* | | | | | | Map to $_FF_ instead of $_DFF_P_ to prevent recursion issuesEddie Hung2019-06-151-13/+13
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* | | | | | | For now, short $_DFF_[NP]_ from ff_map.v at re-integrationEddie Hung2019-06-151-0/+8
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* | | | | | Get rid of compiler warningsEddie Hung2019-06-141-5/+5
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* | | | | | Update abc9 -D docEddie Hung2019-06-141-1/+2
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* | | | | | Enable "abc9 -D <num>" for timing-driven synthesisEddie Hung2019-06-141-9/+9
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* | | | | | Further cleanup based on @daveshah1Eddie Hung2019-06-141-10/+0
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* | | | | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaigEddie Hung2019-06-141-0/+9
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| * | | | | | ecp5: Add abc9 optionDavid Shah2019-06-141-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | Remove extra semicolonEddie Hung2019-06-141-1/+1
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* | | | | | Rip out all non FPGA stuff from abc9Eddie Hung2019-06-121-343/+111
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* | | | | | Fix spellingEddie Hung2019-06-121-1/+1
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* | | | | | Revert "For 'stat' do not count modules with abc_box_id"Eddie Hung2019-06-121-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit b89bb744529fc8a5e4cd38522f86a797117f2abc.
* | | | | | Be more precise when connecting during ABC9 re-integrationEddie Hung2019-06-121-1/+3
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