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* formalff: Fix crash with _NOT_ gates in -hierarchy modeJannis Harder2023-01-251-1/+1
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* Merge pull request #3624 from jix/sim_ywMiodrag Milanović2023-01-234-40/+680
|\ | | | | Changes to support SBY trace generation with the sim command
| * sim/formalff: Clock handling for yw cosimJannis Harder2023-01-112-21/+246
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| * sim: Improvements and fixes for yw cosimJannis Harder2023-01-111-4/+91
| | | | | | | | | | | | * Fixed $cover handling * Improved sparse memory handling when writing traces * JSON summary output
| * sim: New -append option for Yosys witness cosimJannis Harder2023-01-111-5/+14
| | | | | | | | This is needed to support SBY's append option.
| * sim: Add Yosys witness (.yw) cosimulationJannis Harder2023-01-111-3/+194
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| * sim: Only check formal cells during gclk simulation updatesJannis Harder2023-01-111-16/+19
| | | | | | | | This is required for compatibility with non-multiclock formal semantics.
| * sim: Internal API to set $initstateJannis Harder2023-01-111-0/+11
| | | | | | | | This is not yet added to any of the simulation drivers.
| * sim: Emit used memory addresses as signals to output tracesJannis Harder2023-01-111-17/+122
| | | | | | | | | | | | | | | | This matches the behavior of smtbmc. This also updates the sim internal memory API to allow masked writes where State::Sa bits (internal don't care - not a valid value for a signal) leave the memory content unchanged.
| * xprop, setundef: Mark xprop decoding bwmuxes, exclude them from setundefJannis Harder2023-01-112-2/+11
| | | | | | | | | | | | | | | | This adds the xprop_decoder attribute to bwmuxes that drive the original unencoded signals. Setundef is changed to ignore the x inputs of these bwmuxes, so that they survive the prep script of SBY's formal flow. This is required to make simulation (via sim) using the prep model show the decoded x signals instead of 0/1 values made up by the solver.
* | Merge pull request #3629 from YosysHQ/micko/clang_fixesMiodrag Milanović2023-01-234-2/+9
|\ \ | | | | | | Fixes for some of clang scan-build detected issues
| * | Fixes for some of clang scan-build detected issuesMiodrag Milanovic2023-01-174-2/+9
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* | show: Remove left-in debug log_warninggatecat2023-01-231-1/+0
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Improve splitcells passClaire Xenia Wolf2023-01-181-52/+120
|/ | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Merge pull request #3605 from gadfort/stat-json-areaN. Engelhardt2023-01-111-0/+3
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| * stat: ensure area is included in json outputPeter Gadfort2022-12-291-0/+3
| | | | | | | | Signed-off-by: Peter Gadfort <peter.gadfort@gmail.com>
* | Merge branch 'master' into claire/eqystuffClaire Xen2023-01-114-36/+36
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| * \ Merge pull request #3537 from jix/xpropJannis Harder2023-01-1110-35/+1508
| |\ \ | | | | | | | | New xprop pass
| * | | Deprecate gcc-4.8Miodrag Milanovic2023-01-114-36/+36
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* | | | Merge branch 'master' of github.com:YosysHQ/yosys into claire/eqystuffClaire Xenia Wolf2023-01-115-5/+25
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| * | | qbfsat support for cvc5, fixes #3608Miodrag Milanovic2023-01-092-3/+7
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| * | formalff: Proper error messages on async inputs for the -clk2ff modeJannis Harder2022-12-091-0/+3
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| * | stat: Fix JSON output for empty designsJannis Harder2022-12-021-2/+2
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| * | tee: Allow logging command output to a given scratchpad valueJannis Harder2022-12-021-0/+13
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* | | Merge branch 'claire/eqystuff' of github.com:YosysHQ/yosys into claire/eqystuffClaire Xenia Wolf2022-12-211-14/+10
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| * | | xprop: Improve signal splitting codeJannis Harder2022-12-121-14/+10
| | | | | | | | | | | | | | | | | | | | Avoid splitting output ports twice when combining -split-outputs with -split-public and clean up the corresponding code.
* | | | Allow non-unique modules without state in sim writeback-modeClaire Xenia Wolf2022-12-211-4/+5
| | | | | | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | | Small bugfix in uniquify passClaire Xenia Wolf2022-12-211-0/+1
|/ / / | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | Improvements in "viz" passClaire Xenia Wolf2022-12-091-24/+100
| | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | Add gold-x handing to miter cross port handlingClaire Xenia Wolf2022-12-081-1/+9
| | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | Merge branch 'claire/eqystuff' of github.com:YosysHQ/yosys into claire/eqystuffClaire Xenia Wolf2022-12-081-0/+39
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| * | | xprop: Add -split-public optionJannis Harder2022-12-081-0/+39
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* | | | Improvements in "viz" commandClaire Xenia Wolf2022-12-071-17/+51
|/ / / | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | Improvements in "viz" passClaire Xenia Wolf2022-12-071-313/+453
| | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | Various improvements in "viz" commandClaire Xenia Wolf2022-12-061-72/+242
| | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | Bugfix in splitcells passClaire Xenia Wolf2022-12-061-5/+13
| | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | Improvements in "viz" commandClaire Xenia Wolf2022-12-041-45/+196
| | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | Add "viz" pass for visualizing big-picture data flow in larger designsClaire Xenia Wolf2022-12-042-0/+511
| | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | Add splitcells passClaire Xenia Wolf2022-12-042-0/+192
| | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | Merge branch 'xprop' of github.com:jix/yosys into claire/eqystuffClaire Xenia Wolf2022-12-0110-35/+1508
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| * | miter: Add -make_cover option to cover each output pair differenceJannis Harder2022-11-301-0/+14
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| * | formalff: Fix -ff2anyinit assertion error for fine FFsJannis Harder2022-11-301-0/+2
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| * | New xprop pass to encode 3-valued x-propagation using 2-valued logicJannis Harder2022-11-302-0/+1199
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| * | sim: Improved global clock handlingJannis Harder2022-11-301-13/+14
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| * | opt_expr: Optimizations for `$bweqx` and `$bwmux`Jannis Harder2022-11-301-0/+63
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| * | Add bwmuxmap passJannis Harder2022-11-302-0/+71
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| * | Add bitwise `$bweqx` and `$bwmux` cellsJannis Harder2022-11-302-6/+29
| | | | | | | | | | | | | | | | | | The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`) cells enable compact encoding and decoding of 3-valued logic signals using multiple 2-valued signals.
| * | opt_expr: Fix shift/shiftx optimizationsJannis Harder2022-11-301-3/+3
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| * | opt_expr: Constant fold mux, pmux, bmux, demux, eqx, nex cellsJannis Harder2022-11-291-0/+33
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| * | opt_expr: Optimize bitwise logic ops with one fully const inputJannis Harder2022-11-291-0/+81
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