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| author | Jannis Harder <me@jix.one> | 2022-12-21 14:39:49 +0100 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2023-01-11 18:07:16 +0100 |
| commit | 9c6198a8272de1558d9f613d52a23c043e1c928a (patch) | |
| tree | c02b968bc6ee5801ea06e5fb93373caf94e65c0f /passes | |
| parent | 44b26d5c6d69999f167d219ef7e9319e48fbc3e9 (diff) | |
| download | yosys-9c6198a8272de1558d9f613d52a23c043e1c928a.tar.gz yosys-9c6198a8272de1558d9f613d52a23c043e1c928a.tar.bz2 yosys-9c6198a8272de1558d9f613d52a23c043e1c928a.zip | |
sim: Internal API to set $initstate
This is not yet added to any of the simulation drivers.
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/sat/sim.cc | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 754fbdf95..86736eeb4 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -153,6 +153,7 @@ struct SimInstance dict<Cell*, ff_state_t> ff_database; dict<IdString, mem_state_t> mem_database; pool<Cell*> formal_database; + pool<Cell*> initstate_database; dict<Cell*, IdString> mem_cells; std::vector<Mem> memories; @@ -256,6 +257,8 @@ struct SimInstance if (cell->type.in(ID($assert), ID($cover), ID($assume))) { formal_database.insert(cell); } + if (cell->type == ID($initstate)) + initstate_database.insert(cell); } if (shared->zinit) @@ -708,6 +711,14 @@ struct SimInstance it.second->update_ph3(); } + void set_initstate_outputs(State state) + { + for (auto cell : initstate_database) + set_state(cell->getPort(ID::Y), state); + for (auto child : children) + child.second->set_initstate_outputs(state); + } + void writeback(pool<Module*> &wbmods) { if (!ff_database.empty() || !mem_database.empty()) { |