Merge pull request #3537 from jix/xprop

New xprop pass

10 files changed, 1508 insertions, 35 deletions

diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc
index 16a38b511..8c7a18d02 100644
--- a/passes/cmds/Makefile.inc
+++ b/passes/cmds/Makefile.inc
@@ -43,3 +43,4 @@ OBJS += passes/cmds/logger.o
 OBJS += passes/cmds/printattrs.o
 OBJS += passes/cmds/sta.o
 OBJS += passes/cmds/clean_zerowidth.o
+OBJS += passes/cmds/xprop.o
diff --git a/passes/cmds/xprop.cc b/passes/cmds/xprop.cc
new file mode 100644
index 000000000..c2a1b5c44
--- /dev/null
+++ b/passes/cmds/xprop.cc
@@ -0,0 +1,1198 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2022  Jannis Harder <jix@yosyshq.com> <me@jix.one>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/celltypes.h"
+#include "kernel/ffinit.h"
+#include "kernel/ff.h"
+#include "kernel/modtools.h"
+#include "kernel/sigtools.h"
+#include "kernel/utils.h"
+#include "kernel/yosys.h"
+#include <deque>
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct XpropOptions
+{
+	bool split_inputs = false;
+	bool split_outputs = false;
+	bool assume_encoding = false;
+	bool assert_encoding = false;
+	bool assume_def_inputs = false;
+	bool required = false;
+	bool formal = false;
+	bool debug_asserts = false;
+};
+
+struct XpropWorker
+{
+	struct EncodedBit {
+		SigBit is_0, is_1, is_x;
+		bool driven;
+	};
+
+	struct EncodedSig {
+		SigSpec is_0, is_1, is_x;
+		Module *module;
+
+		void invert() { std::swap(is_0, is_1); }
+		void auto_0() { connect_0(module->Not(NEW_ID, module->Or(NEW_ID, is_1, is_x))); }
+		void auto_1() { connect_1(module->Not(NEW_ID, module->Or(NEW_ID, is_0, is_x))); }
+		void auto_x() { connect_x(module->Not(NEW_ID, module->Or(NEW_ID, is_0, is_1))); }
+
+		void connect_0(SigSpec sig) { module->connect(is_0, sig); }
+		void connect_1(SigSpec sig) { module->connect(is_1, sig); }
+		void connect_x(SigSpec sig) { module->connect(is_x, sig); }
+
+		void connect_1_under_x(SigSpec sig) { connect_1(module->And(NEW_ID, sig, module->Not(NEW_ID, is_x))); }
+		void connect_0_under_x(SigSpec sig) { connect_0(module->And(NEW_ID, sig, module->Not(NEW_ID, is_x))); }
+
+		void connect_x_under_0(SigSpec sig) { connect_x(module->And(NEW_ID, sig, module->Not(NEW_ID, is_0))); }
+
+		void connect_as_bool() {
+			int width = GetSize(is_0);
+			if (width <= 1)
+				return;
+			module->connect(is_0.extract(1, width - 1), Const(State::S1, width - 1));
+			module->connect(is_1.extract(1, width - 1), Const(State::S0, width - 1));
+			module->connect(is_x.extract(1, width - 1), Const(State::S0, width - 1));
+			is_0 = is_0[0];
+			is_1 = is_1[0];
+			is_x = is_x[0];
+		}
+
+		int size() const { return is_0.size(); }
+	};
+
+	Module *module;
+	XpropOptions options;
+	ModWalker modwalker;
+	SigMap &sigmap;
+	FfInitVals initvals;
+
+	pool<SigBit> maybe_x_bits;
+	dict<SigBit, EncodedBit> encoded_bits;
+
+	pool<Cell *> pending_cells;
+	std::deque<Cell *> pending_cell_queue;
+
+	XpropWorker(Module *module, XpropOptions options) :
+		module(module), options(options),
+		modwalker(module->design), sigmap(modwalker.sigmap)
+	{
+		modwalker.setup(module);
+		initvals.set(&modwalker.sigmap, module);
+
+		maybe_x_bits.insert(State::Sx);
+
+		for (auto cell : module->cells()) {
+			pending_cells.insert(cell);
+			pending_cell_queue.push_back(cell);
+		}
+
+		if (!options.assume_def_inputs) {
+			for (auto port : module->ports) {
+				auto wire = module->wire(port);
+				if (wire->port_input)
+					mark_maybe_x(SigSpec(wire));
+			}
+		}
+	}
+
+	bool maybe_x(SigBit bit)
+	{
+		return maybe_x_bits.count(sigmap(bit));
+	}
+
+	bool maybe_x(const SigSpec &sig)
+	{
+		for (auto bit : sig)
+			if (maybe_x(bit)) return true;
+		return false;
+	}
+
+	bool ports_maybe_x(Cell *cell)
+	{
+		for (auto &conn : cell->connections())
+			if (maybe_x(conn.second))
+				return true;
+		return false;
+	}
+
+	bool inputs_maybe_x(Cell *cell)
+	{
+		for (auto &conn : cell->connections())
+			if (cell->input(conn.first) && maybe_x(conn.second))
+				return true;
+		return false;
+	}
+
+	void mark_maybe_x(SigBit bit)
+	{
+		sigmap.apply(bit);
+		if (!maybe_x_bits.insert(bit).second)
+			return;
+		auto it = modwalker.signal_consumers.find(bit);
+		if (it == modwalker.signal_consumers.end())
+			return;
+		for (auto &consumer : it->second)
+			if (pending_cells.insert(consumer.cell).second)
+				pending_cell_queue.push_back(consumer.cell);
+	}
+
+	void mark_maybe_x(const SigSpec &sig)
+	{
+		for (auto bit : sig)
+			mark_maybe_x(bit);
+	}
+
+	void mark_outputs_maybe_x(Cell *cell)
+	{
+		for (auto &conn : cell->connections())
+			if (cell->output(conn.first))
+				mark_maybe_x(conn.second);
+	}
+
+	EncodedSig encoded(SigSpec sig, bool driving = false)
+	{
+		EncodedSig result;
+		SigSpec invert;
+
+		if (driving)
+			result.module = module;
+
+		int new_bits = 0;
+
+		sigmap.apply(sig);
+
+		for (auto bit : sig) {
+			if (!bit.is_wire())
+				continue;
+			else if (!maybe_x(bit) && !driving)
+				invert.append(bit);
+			else if (!encoded_bits.count(bit)) {
+				new_bits += 1;
+				encoded_bits.emplace(bit, {
+					State::Sm, State::Sm, State::Sm, false
+				});
+			}
+		}
+
+		if (!invert.empty() && !driving)
+			invert = module->Not(NEW_ID, invert);
+
+		EncodedSig new_sigs;
+		if (new_bits > 0) {
+			new_sigs.is_0 = module->addWire(NEW_ID, new_bits);
+			new_sigs.is_1 = module->addWire(NEW_ID, new_bits);
+			new_sigs.is_x = module->addWire(NEW_ID, new_bits);
+		}
+
+		int invert_pos = 0;
+		int new_pos = 0;
+
+		SigSpec driven_orig;
+		EncodedSig driven_enc;
+		SigSig driven_never_x;
+
+		for (auto bit : sig)
+		{
+			if (!bit.is_wire()) {
+				result.is_0.append(bit == State::S0 ? State::S1 : State::S0);
+				result.is_1.append(bit == State::S1 ? State::S1 : State::S0);
+				result.is_x.append(bit == State::Sx ? State::S1 : State::S0);
+				continue;
+			} else if (!maybe_x(bit) && !driving) {
+				result.is_0.append(invert[invert_pos++]);
+				result.is_1.append(bit);
+				result.is_x.append(State::S0);
+				continue;
+			}
+			auto &enc = encoded_bits.at(bit);
+			if (enc.is_0 == State::Sm) {
+				enc.is_0 = new_sigs.is_0[new_pos];
+				enc.is_1 = new_sigs.is_1[new_pos];
+				enc.is_x = new_sigs.is_x[new_pos];
+				new_pos++;
+			}
+			if (driving) {
+				log_assert(!enc.driven);
+				enc.driven = true;
+				if (maybe_x(bit)) {
+					driven_orig.append(bit);
+					driven_enc.is_0.append(enc.is_0);
+					driven_enc.is_1.append(enc.is_1);
+					driven_enc.is_x.append(enc.is_x);
+				} else {
+					driven_never_x.first.append(bit);
+					driven_never_x.second.append(enc.is_1);
+				}
+			}
+			result.is_0.append(enc.is_0);
+			result.is_1.append(enc.is_1);
+			result.is_x.append(enc.is_x);
+		}
+
+		if (!driven_orig.empty()) {
+			module->addBwmux(NEW_ID, driven_enc.is_1, Const(State::Sx, GetSize(driven_orig)), driven_enc.is_x, driven_orig);
+		}
+		if (!driven_never_x.first.empty()) {
+			module->connect(driven_never_x);
+		}
+
+		if (driving && (options.assert_encoding || options.assume_encoding)) {
+			auto not_0 = module->Not(NEW_ID, result.is_0);
+			auto not_1 = module->Not(NEW_ID, result.is_1);
+			auto not_x = module->Not(NEW_ID, result.is_x);
+			auto valid = module->ReduceAnd(NEW_ID, {
+				module->Eq(NEW_ID, result.is_0, module->And(NEW_ID, not_1, not_x)),
+				module->Eq(NEW_ID, result.is_1, module->And(NEW_ID, not_0, not_x)),
+				module->Eq(NEW_ID, result.is_x, module->And(NEW_ID, not_0, not_1)),
+			});
+			if (options.assert_encoding)
+				module->addAssert(NEW_ID_SUFFIX("xprop_enc"), valid, State::S1);
+			else
+				module->addAssume(NEW_ID_SUFFIX("xprop_enc"), valid, State::S1);
+			if (options.debug_asserts) {
+				auto bad_bits = module->Bweqx(NEW_ID, {result.is_0, result.is_1, result.is_x}, Const(State::Sx, GetSize(result) * 3));
+				module->addAssert(NEW_ID_SUFFIX("xprop_debug"), module->LogicNot(NEW_ID, bad_bits), State::S1);
+			}
+		}
+
+		return result;
+	}
+
+	void mark_all_maybe_x()
+	{
+		while (!pending_cell_queue.empty()) {
+			Cell *cell = pending_cell_queue.front();
+			pending_cell_queue.pop_front();
+			pending_cells.erase(cell);
+
+			mark_maybe_x(cell);
+		}
+	}
+
+	void mark_maybe_x(Cell *cell) {
+		if (cell->type.in(ID($bweqx), ID($eqx), ID($nex), ID($initstate), ID($assert), ID($assume), ID($cover), ID($anyseq), ID($anyconst)))
+			return;
+
+		if (cell->type.in(ID($pmux))) {
+			mark_outputs_maybe_x(cell);
+			return;
+		}
+
+		if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) {
+			FfData ff(&initvals, cell);
+
+			if (cell->type != ID($anyinit))
+				for (int i = 0; i < ff.width; i++)
+					if (ff.val_init[i] == State::Sx)
+						mark_maybe_x(ff.sig_q[i]);
+
+			for (int i = 0; i < ff.width; i++)
+				if (maybe_x(ff.sig_d[i]))
+					mark_maybe_x(ff.sig_q[i]);
+
+			if ((ff.has_clk || ff.has_gclk) && !ff.has_ce && !ff.has_aload && !ff.has_srst && !ff.has_arst && !ff.has_sr)
+				return;
+		}
+
+		if (cell->type == ID($not)) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto sig_a = cell->getPort(ID::A); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
+			for (int i = 0; i < GetSize(sig_y); i++)
+				if (maybe_x(sig_a[i]))
+					mark_maybe_x(sig_y[i]);
+			return;
+		}
+
+		if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto sig_a = cell->getPort(ID::A); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
+			auto sig_b = cell->getPort(ID::B); sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
+			for (int i = 0; i < GetSize(sig_y); i++)
+				if (maybe_x(sig_a[i]) || maybe_x(sig_b[i]))
+					mark_maybe_x(sig_y[i]);
+			return;
+		}
+
+		if (cell->type.in(ID($bwmux))) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto &sig_a = cell->getPort(ID::A);
+			auto &sig_b = cell->getPort(ID::B);
+			auto &sig_s = cell->getPort(ID::S);
+			for (int i = 0; i < GetSize(sig_y); i++)
+				if (maybe_x(sig_a[i]) || maybe_x(sig_b[i]) || maybe_x(sig_s[i]))
+					mark_maybe_x(sig_y[i]);
+			return;
+		}
+
+		if (cell->type.in(ID($_MUX_), ID($mux), ID($bmux))) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto &sig_a = cell->getPort(ID::A);
+			auto &sig_b = cell->getPort(ID::B);
+			auto &sig_s = cell->getPort(ID::S);
+			if (maybe_x(sig_s)) {
+				mark_maybe_x(sig_y);
+				return;
+			}
+			for (int i = 0; i < GetSize(sig_y); i++) {
+				if (maybe_x(sig_a[i])) {
+					mark_maybe_x(sig_y[i]);
+					continue;
+				}
+				for (int j = i; j < GetSize(sig_b); j += GetSize(sig_y)) {
+					if (maybe_x(sig_b[j])) {
+						mark_maybe_x(sig_y[i]);
+						break;
+					}
+				}
+			}
+			return;
+		}
+
+		if (cell->type.in(ID($demux))) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto &sig_a = cell->getPort(ID::A);
+			auto &sig_s = cell->getPort(ID::S);
+			if (maybe_x(sig_s)) {
+				mark_maybe_x(sig_y);
+				return;
+			}
+			for (int i = 0; i < GetSize(sig_a); i++)
+				if (maybe_x(sig_a[i]))
+					for (int j = i; j < GetSize(sig_y); j += GetSize(sig_a))
+						mark_maybe_x(sig_y[j]);
+			return;
+		}
+
+		if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift))) {
+			auto &sig_b = cell->getPort(ID::B);
+			auto &sig_y = cell->getPort(ID::Y);
+
+			if (maybe_x(sig_b)) {
+				mark_maybe_x(sig_y);
+				return;
+			}
+
+			auto &sig_a = cell->getPort(ID::A);
+
+			if (maybe_x(sig_a)) {
+				// We could be more precise for shifts, but that's not required
+				// for correctness, so let's keep it simple
+				mark_maybe_x(sig_y);
+				return;
+			}
+			return;
+		}
+
+		if (cell->type.in(ID($shiftx))) {
+			auto &sig_b = cell->getPort(ID::B);
+			auto &sig_y = cell->getPort(ID::Y);
+
+			if (cell->getParam(ID::B_SIGNED).as_bool() || GetSize(sig_b) >= 30) {
+				mark_maybe_x(sig_y);
+			} else {
+				int max_shift = (1 << GetSize(sig_b)) - 1;
+
+				auto &sig_a = cell->getPort(ID::A);
+
+				for (int i = 0; i < GetSize(sig_y); i++)
+					if (i + max_shift >= GetSize(sig_a))
+						mark_maybe_x(sig_y[i]);
+			}
+
+			if (maybe_x(sig_b)) {
+				mark_maybe_x(sig_y);
+				return;
+			}
+
+			auto &sig_a = cell->getPort(ID::A);
+			if (maybe_x(sig_a)) {
+				// We could be more precise for shifts, but that's not required
+				// for correctness, so let's keep it simple
+				mark_maybe_x(sig_y);
+				return;
+			}
+			return;
+		}
+
+		if (cell->type.in(ID($add), ID($sub), ID($mul), ID($neg))) {
+			if (inputs_maybe_x(cell))
+				mark_outputs_maybe_x(cell);
+			return;
+		}
+
+		if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
+			mark_outputs_maybe_x(cell);
+			return;
+		}
+
+		if (cell->type.in(
+			ID($le), ID($lt), ID($ge), ID($gt),
+			ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor),
+			ID($reduce_bool), ID($logic_not), ID($logic_or), ID($logic_and),
+			ID($eq), ID($ne),
+
+			ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_ANDNOT_), ID($_OR_), ID($_NOR_), ID($_ORNOT_), ID($_XOR_), ID($_XNOR_)
+		)) {
+			auto &sig_y = cell->getPort(ID::Y);
+			if (inputs_maybe_x(cell))
+				mark_maybe_x(sig_y[0]);
+			return;
+		}
+
+		log_warning("Unhandled cell %s (%s) during maybe-x marking\n", log_id(cell), log_id(cell->type));
+		mark_outputs_maybe_x(cell);
+	}
+
+	void process_cells()
+	{
+		for (auto cell : module->selected_cells())
+			process_cell(cell);
+	}
+
+	void process_cell(Cell *cell)
+	{
+		if (!ports_maybe_x(cell)) {
+
+			if (cell->type == ID($bweq)) {
+				auto sig_y = cell->getPort(ID::Y);
+				auto sig_a = cell->getPort(ID::A);
+				auto sig_b = cell->getPort(ID::B);
+
+				auto name = cell->name;
+				module->remove(cell);
+				module->addXnor(name, sig_a, sig_b, sig_y);
+				return;
+			}
+
+			if (cell->type.in(ID($nex), ID($eqx))) {
+				auto sig_y = cell->getPort(ID::Y);
+				auto sig_a = cell->getPort(ID::A);
+				auto sig_b = cell->getPort(ID::B);
+
+				auto name = cell->name;
+				module->remove(cell);
+				if (cell->type == ID($eqx))
+					module->addEq(name, sig_a, sig_b, sig_y);
+				else
+					module->addNe(name, sig_a, sig_b, sig_y);
+				return;
+			}
+
+			return;
+		}
+
+		if (cell->type.in(ID($not), ID($_NOT_))) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto sig_a = cell->getPort(ID::A);
+			if (cell->type == ID($not))
+				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
+
+			auto enc_a = encoded(sig_a);
+			auto enc_y = encoded(sig_y, true);
+
+			enc_y.connect_x(enc_a.is_x);
+			enc_y.connect_0(enc_a.is_1);
+			enc_y.connect_1(enc_a.is_0);
+
+			module->remove(cell);
+			return;
+		}
+
+		if (cell->type.in(ID($and), ID($or), ID($_AND_), ID($_OR_), ID($_NAND_), ID($_NOR_), ID($_ANDNOT_), ID($_ORNOT_))) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto sig_a = cell->getPort(ID::A);
+			auto sig_b = cell->getPort(ID::B);
+			if (cell->type.in(ID($and), ID($or))) {
+				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
+				sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
+			}
+
+			auto enc_a = encoded(sig_a);
+			auto enc_b = encoded(sig_b);
+			auto enc_y = encoded(sig_y, true);
+
+			if (cell->type.in(ID($or), ID($_OR_)))
+				enc_a.invert(), enc_b.invert(), enc_y.invert();
+			if (cell->type.in(ID($_NAND_), ID($_NOR_)))
+				enc_y.invert();
+			if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
+				enc_b.invert();
+
+			enc_y.connect_0(module->Or(NEW_ID, enc_a.is_0, enc_b.is_0));
+			enc_y.connect_1(module->And(NEW_ID, enc_a.is_1, enc_b.is_1));
+			enc_y.auto_x();
+			module->remove(cell);
+			return;
+		}
+
+		if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($logic_not))) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto &sig_a = cell->getPort(ID::A);
+
+			auto enc_a = encoded(sig_a);
+			auto enc_y = encoded(sig_y, true);
+
+			enc_y.connect_as_bool();
+
+			if (cell->type.in(ID($reduce_or), ID($reduce_bool)))
+				enc_a.invert(), enc_y.invert();
+			if (cell->type == ID($logic_not))
+				enc_a.invert();
+
+			enc_y.connect_0(module->ReduceOr(NEW_ID, enc_a.is_0));
+			enc_y.connect_1(module->ReduceAnd(NEW_ID, enc_a.is_1));
+			enc_y.auto_x();
+			module->remove(cell);
+
+			return;
+		}
+
+		if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto &sig_a = cell->getPort(ID::A);
+
+			auto enc_a = encoded(sig_a);
+			auto enc_y = encoded(sig_y, true);
+
+			enc_y.connect_as_bool();
+			if (cell->type == ID($reduce_xnor))
+				enc_y.invert();
+
+
+			enc_y.connect_x(module->ReduceOr(NEW_ID, enc_a.is_x));
+			enc_y.connect_1_under_x(module->ReduceXor(NEW_ID, enc_a.is_1));
+			enc_y.auto_0();
+			module->remove(cell);
+
+			return;
+		}
+
+		if (cell->type.in(ID($logic_and), ID($logic_or))) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto &sig_a = cell->getPort(ID::A);
+			auto &sig_b = cell->getPort(ID::B);
+
+			auto enc_a = encoded(sig_a);
+			auto enc_b = encoded(sig_b);
+			auto enc_y = encoded(sig_y, true);
+
+			enc_y.connect_as_bool();
+
+			auto a_is_1 = module->ReduceOr(NEW_ID, enc_a.is_1);
+			auto a_is_0 = module->ReduceAnd(NEW_ID, enc_a.is_0);
+			auto b_is_1 = module->ReduceOr(NEW_ID, enc_b.is_1);
+			auto b_is_0 = module->ReduceAnd(NEW_ID, enc_b.is_0);
+
+			if (cell->type == ID($logic_or))
+				 enc_y.invert(), std::swap(a_is_0, a_is_1), std::swap(b_is_0, b_is_1);
+
+			enc_y.connect_0(module->Or(NEW_ID, a_is_0, b_is_0));
+			enc_y.connect_1(module->And(NEW_ID, a_is_1, b_is_1));
+			enc_y.auto_x();
+			module->remove(cell);
+			return;
+		}
+
+		if (cell->type.in(ID($xor), ID($xnor), ID($_XOR_), ID($_XNOR_))) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto sig_a = cell->getPort(ID::A);
+			auto sig_b = cell->getPort(ID::B);
+			if (cell->type.in(ID($xor), ID($xnor))) {
+				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
+				sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
+			}
+
+			auto enc_a = encoded(sig_a);
+			auto enc_b = encoded(sig_b);
+			auto enc_y = encoded(sig_y, true);
+
+			if (cell->type.in(ID($xnor), ID($_XNOR_)))
+				enc_y.invert();
+
+			enc_y.connect_x(module->Or(NEW_ID, enc_a.is_x, enc_b.is_x));
+			enc_y.connect_1_under_x(module->Xor(NEW_ID, enc_a.is_1, enc_b.is_1));
+			enc_y.auto_0();
+			module->remove(cell);
+			return;
+		}
+
+		if (cell->type.in(ID($eq), ID($ne))) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto sig_a = cell->getPort(ID::A);
+			auto sig_b = cell->getPort(ID::B);
+			int width = std::max(GetSize(sig_a), GetSize(sig_b));
+			sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool());
+			sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool());
+
+			auto enc_a = encoded(sig_a);
+			auto enc_b = encoded(sig_b);
+			auto enc_y = encoded(sig_y, true);
+			enc_y.connect_as_bool();
+
+			if (cell->type == ID($ne))
+				enc_y.invert();
+
+			auto delta = module->Xor(NEW_ID, enc_a.is_1, enc_b.is_1);
+			auto xpos = module->Or(NEW_ID, enc_a.is_x, enc_b.is_x);
+
+			enc_y.connect_0(module->ReduceOr(NEW_ID, module->And(NEW_ID, delta, module->Not(NEW_ID, xpos))));
+			enc_y.connect_x_under_0(module->ReduceOr(NEW_ID, xpos));
+			enc_y.auto_1();
+			module->remove(cell);
+			return;
+		}
+
+		if (cell->type.in(ID($eqx), ID($nex))) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto sig_a = cell->getPort(ID::A);
+			auto sig_b = cell->getPort(ID::B);
+			int width = std::max(GetSize(sig_a), GetSize(sig_b));
+			sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool());
+			sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool());
+
+			auto enc_a = encoded(sig_a);
+			auto enc_b = encoded(sig_b);
+
+			auto delta_0 = module->Xnor(NEW_ID, enc_a.is_0, enc_b.is_0);
+			auto delta_1 = module->Xnor(NEW_ID, enc_a.is_1, enc_b.is_1);
+
+			auto eq = module->ReduceAnd(NEW_ID, {delta_0, delta_1});
+
+			auto res = cell->type == ID($nex) ? module->Not(NEW_ID, eq) : eq;
+
+			module->connect(sig_y[0], res);
+			if (GetSize(sig_y) > 1)
+				module->connect(sig_y.extract(1, GetSize(sig_y) - 1), Const(State::S0, GetSize(sig_y) - 1));
+			module->remove(cell);
+			return;
+		}
+
+		if (cell->type.in(ID($bweqx))) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto &sig_a = cell->getPort(ID::A);
+			auto &sig_b = cell->getPort(ID::B);
+
+			auto enc_a = encoded(sig_a);
+			auto enc_b = encoded(sig_b);
+
+			auto delta_0 = module->Xnor(NEW_ID, enc_a.is_0, enc_b.is_0);
+			auto delta_1 = module->Xnor(NEW_ID, enc_a.is_1, enc_b.is_1);
+			module->addAnd(NEW_ID, delta_0, delta_1, sig_y);
+			module->remove(cell);
+			return;
+		}
+
+		if (cell->type.in(ID($_MUX_), ID($mux), ID($bwmux))) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto &sig_a = cell->getPort(ID::A);
+			auto &sig_b = cell->getPort(ID::B);
+			auto sig_s = cell->getPort(ID::S);
+
+			if (cell->type == ID($mux))
+				sig_s = SigSpec(sig_s[0], GetSize(sig_y));
+
+			auto enc_a = encoded(sig_a);
+			auto enc_b = encoded(sig_b);
+			auto enc_s = encoded(sig_s);
+			auto enc_y = encoded(sig_y, true);
+
+			enc_y.connect_1(module->And(NEW_ID,
+					module->Or(NEW_ID, enc_a.is_1, enc_s.is_1),
+					module->Or(NEW_ID, enc_b.is_1, enc_s.is_0)));
+			enc_y.connect_0(module->And(NEW_ID,
+					module->Or(NEW_ID, enc_a.is_0, enc_s.is_1),
+					module->Or(NEW_ID, enc_b.is_0, enc_s.is_0)));
+			enc_y.auto_x();
+			module->remove(cell);
+			return;
+		}
+
+		if (cell->type.in(ID($pmux))) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto &sig_a = cell->getPort(ID::A);
+			auto &sig_b = cell->getPort(ID::B);
+			auto &sig_s = cell->getPort(ID::S);
+
+			auto enc_a = encoded(sig_a);
+			auto enc_b = encoded(sig_b);
+			auto enc_s = encoded(sig_s);
+			auto enc_y = encoded(sig_y, true);
+
+			int width = GetSize(enc_y);
+
+			auto all_x = module->ReduceOr(NEW_ID, {
+				enc_s.is_x,
+				module->And(NEW_ID, enc_s.is_1, module->Sub(NEW_ID, enc_s.is_1, Const(1, width)))
+			});
+
+			auto selected = enc_a;
+
+			for (int i = 0; i < GetSize(enc_s); i++) {
+				auto sel_bit = enc_s.is_1[i];
+				selected.is_0 = module->Mux(NEW_ID, selected.is_0, enc_b.is_0.extract(i * width, width), sel_bit);
+				selected.is_1 = module->Mux(NEW_ID, selected.is_1, enc_b.is_1.extract(i * width, width), sel_bit);
+				selected.is_x = module->Mux(NEW_ID, selected.is_x, enc_b.is_x.extract(i * width, width), sel_bit);
+			}
+
+			enc_y.connect_0(module->Mux(NEW_ID, selected.is_0, Const(State::S0, width), all_x));
+			enc_y.connect_1(module->Mux(NEW_ID, selected.is_1, Const(State::S0, width), all_x));
+			enc_y.connect_x(module->Mux(NEW_ID, selected.is_x, Const(State::S1, width), all_x));
+
+			module->remove(cell);
+			return;
+		}
+
+		if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) {
+			auto &sig_y = cell->getPort(ID::Y);
+			auto &sig_a = cell->getPort(ID::A);
+			auto &sig_b = cell->getPort(ID::B);
+
+			auto enc_a = encoded(sig_a);
+			auto enc_b = encoded(sig_b);
+			auto enc_y = encoded(sig_y, true);
+
+			auto all_x = module->ReduceOr(NEW_ID, enc_b.is_x)[0];
+			auto not_all_x = module->Not(NEW_ID, all_x)[0];
+
+			SigSpec y_not_0 = module->addWire(NEW_ID, GetSize(sig_y));
+			SigSpec y_1 = module->addWire(NEW_ID, GetSize(sig_y));
+			SigSpec y_x = module->addWire(NEW_ID, GetSize(sig_y));
+
+			auto encoded_type = cell->type == ID($shiftx) ? ID($shift) : cell->type;
+
+			if (cell->type == ID($shiftx)) {
+				std::swap(enc_a.is_0, enc_a.is_x);
+			}
+
+			auto shift_0 = module->addCell(NEW_ID, encoded_type);
+			shift_0->parameters = cell->parameters;
+			shift_0->setPort(ID::A, module->Not(NEW_ID, enc_a.is_0));
+			shift_0->setPort(ID::B, enc_b.is_1);
+			shift_0->setPort(ID::Y, y_not_0);
+
+			auto shift_1 = module->addCell(NEW_ID, encoded_type);
+			shift_1->parameters = cell->parameters;
+			shift_1->setPort(ID::A, enc_a.is_1);
+			shift_1->setPort(ID::B, enc_b.is_1);
+			shift_1->setPort(ID::Y, y_1);
+
+			auto shift_x = module->addCell(NEW_ID, encoded_type);
+			shift_x->parameters = cell->parameters;
+			shift_x->setPort(ID::A, enc_a.is_x);
+			shift_x->setPort(ID::B, enc_b.is_1);
+			shift_x->setPort(ID::Y, y_x);
+
+			SigSpec y_0 = module->Not(NEW_ID, y_not_0);
+
+			if (cell->type == ID($shiftx))
+				std::swap(y_0, y_x);
+
+			enc_y.connect_0(module->And(NEW_ID, y_0, SigSpec(not_all_x, GetSize(sig_y))));
+			enc_y.connect_1(module->And(NEW_ID, y_1, SigSpec(not_all_x, GetSize(sig_y))));
+			enc_y.connect_x(module->Or(NEW_ID, y_x, SigSpec(all_x, GetSize(sig_y))));
+
+			module->remove(cell);
+			return;
+		}
+
+		if (cell->type.in(ID($ff))) {
+			auto &sig_d = cell->getPort(ID::D);
+			auto &sig_q = cell->getPort(ID::Q);
+
+			auto init_q = initvals(sig_q);
+			auto init_q_is_1 = init_q;
+			auto init_q_is_x = init_q;
+
+			for (auto &bit : init_q_is_1)
+				bit = bit == State::S1 ? State::S1 : State::S0;
+			for (auto &bit : init_q_is_x)
+				bit = bit == State::Sx ? State::S1 : State::S0;
+
+			initvals.remove_init(sig_q);
+
+			auto enc_d = encoded(sig_d);
+			auto enc_q = encoded(sig_q, true);
+
+			auto data_q = module->addWire(NEW_ID, GetSize(sig_q));
+
+			module->addFf(NEW_ID, enc_d.is_1, data_q);
+			module->addFf(NEW_ID, enc_d.is_x, enc_q.is_x);
+
+			initvals.set_init(data_q, init_q_is_1);
+			initvals.set_init(enc_q.is_x, init_q_is_x);
+
+			enc_q.connect_1_under_x(data_q);
+			enc_q.auto_0();
+
+			module->remove(cell);
+			return;
+		}
+
+		if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) {
+			FfData ff(&initvals, cell);
+
+			if ((ff.has_clk || ff.has_gclk) && !ff.has_ce && !ff.has_aload && !ff.has_srst && !ff.has_arst && !ff.has_sr) {
+				if (ff.has_clk && maybe_x(ff.sig_clk)) {
+					log_warning("Only non-x CLK inputs are currently supported for %s (%s)\n", log_id(cell), log_id(cell->type));
+				} else {
+					auto init_q = ff.val_init;
+					auto init_q_is_1 = init_q;
+					auto init_q_is_x = init_q;
+
+					if (ff.is_anyinit) {
+						for (auto &bit : init_q_is_1)
+							bit = State::Sx;
+						for (auto &bit : init_q_is_x)
+							bit = State::S0;
+					} else {
+						for (auto &bit : init_q_is_1)
+							bit = bit == State::S1 ? State::S1 : State::S0;
+						for (auto &bit : init_q_is_x)
+							bit = bit == State::Sx ? State::S1 : State::S0;
+					}
+
+					ff.remove();
+
+					auto enc_d = encoded(ff.sig_d);
+					auto enc_q = encoded(ff.sig_q, true);
+
+					auto data_q = module->addWire(NEW_ID, GetSize(ff.sig_q));
+
+					ff.sig_d = enc_d.is_1;
+					ff.sig_q = data_q;
+					ff.val_init = init_q_is_1;
+					ff.emit();
+
+					ff.name = NEW_ID;
+					ff.cell = nullptr;
+					ff.sig_d = enc_d.is_x;
+					ff.sig_q = enc_q.is_x;
+					ff.is_anyinit = false;
+					ff.val_init = init_q_is_x;
+					ff.emit();
+
+
+					enc_q.connect_1_under_x(data_q);
+					enc_q.auto_0();
+
+					return;
+				}
+			} else {
+				log_warning("Unhandled FF-cell %s (%s), consider running clk2fflogic, async2sync and/or dffunmap\n", log_id(cell), log_id(cell->type));
+			}
+		}
+
+		// Celltypes where any input x bit makes the whole output x
+		if (cell->type.in(
+			ID($neg),
+			ID($le), ID($lt), ID($ge), ID($gt),
+			ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor)
+		)) {
+
+			SigSpec inbits_x;
+			for (auto &conn : cell->connections()) {
+				if (cell->input(conn.first)) {
+					auto enc_port = encoded(conn.second);
+					inbits_x.append(enc_port.is_x);
+					cell->setPort(conn.first, enc_port.is_1);
+				}
+			}
+
+			if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
+				auto sig_b = cell->getPort(ID::B);
+				auto invalid = module->LogicNot(NEW_ID, sig_b);
+				inbits_x.append(invalid);
+				sig_b[0] = module->Or(NEW_ID, sig_b[0], invalid);
+				cell->setPort(ID::B, sig_b);
+			}
+
+			SigBit outbits_x = (GetSize(inbits_x) == 1 ? inbits_x : module->ReduceOr(NEW_ID, inbits_x));
+
+			bool bool_out = cell->type.in(ID($le), ID($lt), ID($ge), ID($gt));
+
+			for (auto &conn : cell->connections()) {
+				if (cell->output(conn.first)) {
+					auto enc_port = encoded(conn.second, true);
+					if (bool_out)
+						enc_port.connect_as_bool();
+
+					SigSpec new_output = module->addWire(NEW_ID, GetSize(conn.second));
+
+					enc_port.connect_1_under_x(bool_out ? new_output.extract(0) : new_output);
+					enc_port.connect_x(SigSpec(outbits_x, GetSize(enc_port)));
+					enc_port.auto_0();
+
+					cell->setPort(conn.first, new_output);
+				}
+			}
+
+			return;
+		}
+
+		if (cell->type == ID($bmux)) // TODO might want to support bmux natively anyway
+			log("Running 'bmuxmap' preserves x-propagation and can be run before 'xprop'.\n");
+		if (cell->type == ID($demux)) // TODO might want to support demux natively anyway
+			log("Running 'demuxmap' preserves x-propagation and can be run before 'xprop'.\n");
+
+		if (options.required)
+			log_error("Unhandled cell %s (%s)\n", log_id(cell), log_id(cell->type));
+		else
+			log_warning("Unhandled cell %s (%s)\n", log_id(cell), log_id(cell->type));
+	}
+
+	void split_ports()
+	{
+		if (!options.split_inputs && !options.split_outputs)
+			return;
+
+		vector<IdString> new_ports;
+
+		for (auto port : module->ports) {
+			auto wire = module->wire(port);
+			if (module->design->selected(module, wire)) {
+				if (wire->port_input == wire->port_output) {
+					log_warning("Port %s not an input or an output port which is not supported by xprop\n", log_id(wire));
+				} else if ((options.split_inputs && !options.assume_def_inputs && wire->port_input) || (options.split_outputs && wire->port_output)) {
+					auto port_d = module->uniquify(stringf("%s_d", port.c_str()));
+					auto port_x = module->uniquify(stringf("%s_x", port.c_str()));
+
+					auto wire_d = module->addWire(port_d, GetSize(wire));
+					auto wire_x = module->addWire(port_x, GetSize(wire));
+
+					wire_d->port_input = wire->port_input;
+					wire_d->port_output = wire->port_output;
+					wire_d->port_id = GetSize(new_ports) + 1;
+
+					wire_x->port_input = wire->port_input;
+					wire_x->port_output = wire->port_output;
+					wire_x->port_id = GetSize(new_ports) + 2;
+
+					if (wire->port_output) {
+						auto enc = encoded(wire);
+						module->connect(wire_d, enc.is_1);
+						module->connect(wire_x, enc.is_x);
+					} else {
+						auto enc = encoded(wire, true);
+
+						enc.connect_x(wire_x);
+						enc.connect_1_under_x(wire_d);
+						enc.auto_0();
+					}
+
+					wire->port_input = wire->port_output = false;
+					wire->port_id = 0;
+
+					new_ports.push_back(port_d);
+					new_ports.push_back(port_x);
+
+					continue;
+				}
+			}
+			wire->port_id = GetSize(new_ports) + 1;
+			new_ports.push_back(port);
+		}
+
+		module->ports = new_ports;
+
+		module->fixup_ports();
+	}
+
+	void encode_remaining()
+	{
+		pool<Wire *> enc_undriven_wires;
+
+		for (auto &enc_bit : encoded_bits) {
+			if (!enc_bit.second.driven) {
+				log_assert(enc_bit.first.is_wire());
+				enc_undriven_wires.insert(enc_bit.first.wire);
+			}
+		}
+
+		if (options.formal && !enc_undriven_wires.empty()) {
+			for (auto &bit : enc_undriven_wires)
+				log_warning("Found encoded wire %s having a non-encoded driver\n", log_signal(bit));
+
+			log_error("Found encoded wires having a non-encoded driver, not allowed in -formal mode\n");
+		}
+
+
+		for (auto wire : enc_undriven_wires) {
+			SigSpec sig(sigmap(wire));
+
+			SigSpec orig;
+			EncodedSig enc;
+
+			for (auto bit : sig) {
+				auto it = encoded_bits.find(bit);
+				if (it == encoded_bits.end() || it->second.driven)
+					continue;
+				orig.append(bit);
+				enc.is_0.append(it->second.is_0);
+				enc.is_1.append(it->second.is_1);
+				enc.is_x.append(it->second.is_x);
+				it->second.driven = true;
+			}
+
+			module->addBweqx(NEW_ID, orig, Const(State::S0, GetSize(orig)), enc.is_0);
+			module->addBweqx(NEW_ID, orig, Const(State::S1, GetSize(orig)), enc.is_1);
+			module->addBweqx(NEW_ID, orig, Const(State::Sx, GetSize(orig)), enc.is_x);
+		}
+	}
+};
+
+struct XpropPass : public Pass {
+	XpropPass() : Pass("xprop", "formal x propagation") {}
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    xprop [options] [selection]\n");
+		log("\n");
+		log("This pass transforms the circuit into an equivalent circuit that explicitly\n");
+		log("encodes the propagation of x values using purely 2-valued logic. On the\n");
+		log("interface between xprop-transformed and non-transformed parts of the design,\n");
+		log("appropriate conversions are inserted automatically.\n");
+		log("\n");
+		log("    -split-inputs\n");
+		log("    -split-outputs\n");
+		log("    -split-ports\n");
+		log("        Replace each input/output/port with two new ports, one carrying the\n");
+		log("        defined values (named <portname>_d) and one carrying the mask of which\n");
+		log("        bits are x (named <portname>_x). When a bit in the <portname>_x is set\n");
+		log("        the corresponding bit in <portname>_d is ignored for inputs and\n");
+		log("        guaranteed to be 0 for outputs.\n");
+		log("\n");
+		log("    -assume-encoding\n");
+		log("        Add encoding invariants as assumptions. This can speed up formal\n");
+		log("        verification tasks.\n");
+		log("\n");
+		log("    -assert-encoding\n");
+		log("        Add encoding invariants as assertions. Used for testing the xprop\n");
+		log("        pass itself.\n");
+		log("\n");
+		log("    -assume-def-inputs\n");
+		log("        Assume all inputs are fully defined. This adds corresponding\n");
+		log("        assumptions to the design and uses these assumptions to optimize the\n");
+		log("        xprop encoding.\n");
+		log("\n");
+		log("    -required\n");
+		log("        Produce a runtime error if any encountered cell could not be encoded.\n");
+		log("\n");
+		log("    -formal\n");
+		log("        Produce a runtime error if any encoded cell uses a signal that is\n");
+		log("		 neither known to be non-x nor driven by another encoded cell.\n");
+		log("\n");
+		log("    -debug-asserts\n");
+		log("        Add assertions checking that the encoding used by this pass never\n");
+		log("        produces x values within the encoded signals.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		XpropOptions options;
+
+		log_header(design, "Executing XPROP pass.\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			if (args[argidx] == "-split-ports") {
+				options.split_inputs = true;
+				options.split_outputs = true;
+				continue;
+			}
+			if (args[argidx] == "-split-inputs") {
+				options.split_inputs = true;
+				continue;
+			}
+			if (args[argidx] == "-split-outputs") {
+				options.split_outputs = true;
+				continue;
+			}
+			if (args[argidx] == "-assume-encoding") {
+				options.assume_encoding = true;
+				continue;
+			}
+			if (args[argidx] == "-assert-encoding") {
+				options.assert_encoding = true;
+				continue;
+			}
+			if (args[argidx] == "-assume-def-inputs") {
+				options.assume_def_inputs = true;
+				continue;
+			}
+			if (args[argidx] == "-required") {
+				options.required = true; // TODO check more
+				continue;
+			}
+			if (args[argidx] == "-formal") {
+				options.formal = true;
+				options.required = true;
+				continue;
+			}
+			if (args[argidx] == "-debug-asserts") { // TODO documented
+				options.debug_asserts = true;
+				options.assert_encoding = true;
+				continue;
+			}
+			break;
+		}
+
+		if (options.assert_encoding && options.assume_encoding)
+			log_cmd_error("The options -assert-encoding and -assume-encoding are exclusive.\n");
+
+		extra_args(args, argidx, design);
+
+		log_push();
+		Pass::call(design, "bmuxmap");
+		Pass::call(design, "demuxmap");
+		log_pop();
+
+		for (auto module : design->selected_modules()) {
+			if (options.assume_def_inputs) {
+				for (auto port : module->ports) {
+					auto wire = module->wire(port);
+					if (!module->design->selected(module, wire))
+						continue;
+
+					if (wire->port_input) {
+						module->addAssume(NEW_ID, module->Not(NEW_ID, module->ReduceOr(NEW_ID, module->Bweqx(NEW_ID, wire, Const(State::Sx, GetSize(wire))))), State::S1);
+					}
+				}
+			}
+
+			XpropWorker worker(module, options);
+			log_debug("Marking all x-bits.\n");
+			worker.mark_all_maybe_x();
+			log_debug("Repalcing cells.\n");
+			worker.process_cells();
+			log_debug("Splitting ports.\n");
+			worker.split_ports();
+			log_debug("Encode remaining signals.\n");
+			worker.encode_remaining();
+
+		}
+	}
+} XpropPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 9cc0170dc..9d5ca4ef9 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -643,6 +643,148 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			goto next_cell;
 		}
 
+		if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor)))
+		{
+			RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
+			RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B));
+
+			bool a_fully_const = (sig_a.is_fully_const() && (!keepdc || !sig_a.is_fully_undef()));
+			bool b_fully_const = (sig_b.is_fully_const() && (!keepdc || !sig_b.is_fully_undef()));
+
+			if (a_fully_const != b_fully_const)
+			{
+				cover("opt.opt_expr.bitwise_logic_one_const");
+				log_debug("Replacing %s cell `%s' in module `%s' having one fully constant input\n",
+						log_id(cell->type), log_id(cell->name), log_id(module));
+				RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y));
+
+				int width = GetSize(cell->getPort(ID::Y));
+
+				sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool());
+				sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool());
+
+				if (!a_fully_const)
+					std::swap(sig_a, sig_b);
+
+				RTLIL::SigSpec b_group_0, b_group_1, b_group_x;
+				RTLIL::SigSpec y_group_0, y_group_1, y_group_x;
+
+				for (int i = 0; i < width; i++) {
+					auto bit_a = sig_a[i].data;
+					if (bit_a == State::S0) b_group_0.append(sig_b[i]), y_group_0.append(sig_y[i]);
+					if (bit_a == State::S1) b_group_1.append(sig_b[i]), y_group_1.append(sig_y[i]);
+					if (bit_a == State::Sx) b_group_x.append(sig_b[i]), y_group_x.append(sig_y[i]);
+				}
+
+				if (cell->type == ID($xnor)) {
+					std::swap(b_group_0, b_group_1);
+					std::swap(y_group_0, y_group_1);
+				}
+
+				RTLIL::SigSpec y_new_0, y_new_1, y_new_x;
+
+				if (cell->type == ID($and)) {
+					if (!y_group_0.empty()) y_new_0 = Const(State::S0, GetSize(y_group_0));
+					if (!y_group_1.empty()) y_new_1 = b_group_1;
+					if (!y_group_x.empty()) {
+						if (keepdc)
+							y_new_x = module->And(NEW_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x);
+						else
+							y_new_x = Const(State::S0, GetSize(y_group_x));
+					}
+				} else if (cell->type == ID($or)) {
+					if (!y_group_0.empty()) y_new_0 = b_group_0;
+					if (!y_group_1.empty()) y_new_1 = Const(State::S1, GetSize(y_group_1));
+					if (!y_group_x.empty()) {
+						if (keepdc)
+							y_new_x = module->Or(NEW_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x);
+						else
+							y_new_x = Const(State::S1, GetSize(y_group_x));
+					}
+				} else if (cell->type.in(ID($xor), ID($xnor))) {
+					if (!y_group_0.empty()) y_new_0 = b_group_0;
+					if (!y_group_1.empty()) y_new_1 = module->Not(NEW_ID, b_group_1);
+					if (!y_group_x.empty()) {
+						if (keepdc)
+							y_new_x = module->Xor(NEW_ID, Const(State::Sx, GetSize(y_group_x)), b_group_x);
+						else // This should be fine even with keepdc, but opt_expr_xor.ys wants to keep the xor
+							y_new_x = Const(State::Sx, GetSize(y_group_x));
+					}
+				} else {
+					log_abort();
+				}
+
+				assign_map.add(y_group_0, y_new_0); module->connect(y_group_0, y_new_0);
+				assign_map.add(y_group_1, y_new_1); module->connect(y_group_1, y_new_1);
+				assign_map.add(y_group_x, y_new_x); module->connect(y_group_x, y_new_x);
+
+				module->remove(cell);
+				did_something = true;
+				goto next_cell;
+			}
+		}
+
+		if (cell->type == ID($bwmux))
+		{
+			RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
+			RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B));
+			RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S));
+			RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y));
+			int width = GetSize(cell->getPort(ID::Y));
+
+			if (sig_s.is_fully_def())
+			{
+				RTLIL::SigSpec a_group_0, b_group_1;
+				RTLIL::SigSpec y_group_0, y_group_1;
+				for (int i = 0; i < width; i++) {
+					if (sig_s[i].data == State::S1)
+						y_group_1.append(sig_y[i]), b_group_1.append(sig_b[i]);
+					else
+						y_group_0.append(sig_y[i]), a_group_0.append(sig_a[i]);
+				}
+
+				assign_map.add(y_group_0, a_group_0); module->connect(y_group_0, a_group_0);
+				assign_map.add(y_group_1, b_group_1); module->connect(y_group_1, b_group_1);
+
+				module->remove(cell);
+				did_something = true;
+				goto next_cell;
+			}
+			else if (sig_a.is_fully_def() || sig_b.is_fully_def())
+			{
+				bool flip = !sig_a.is_fully_def();
+				if (flip)
+					std::swap(sig_a, sig_b);
+
+				RTLIL::SigSpec b_group_0, b_group_1;
+				RTLIL::SigSpec s_group_0, s_group_1;
+				RTLIL::SigSpec y_group_0, y_group_1;
+				for (int i = 0; i < width; i++) {
+					if (sig_a[i].data == State::S1)
+						y_group_1.append(sig_y[i]), b_group_1.append(sig_b[i]), s_group_1.append(sig_s[i]);
+					else
+						y_group_0.append(sig_y[i]), b_group_0.append(sig_b[i]), s_group_0.append(sig_s[i]);
+				}
+
+				RTLIL::SigSpec y_new_0, y_new_1;
+
+				if (flip) {
+					if (!y_group_0.empty()) y_new_0 = module->And(NEW_ID, b_group_0, module->Not(NEW_ID, s_group_0));
+					if (!y_group_1.empty()) y_new_1 = module->Or(NEW_ID, b_group_1, s_group_1);
+				} else {
+					if (!y_group_0.empty()) y_new_0 = module->And(NEW_ID, b_group_0, s_group_0);
+					if (!y_group_1.empty()) y_new_1 = module->Or(NEW_ID, b_group_1, module->Not(NEW_ID, s_group_1));
+				}
+
+				module->connect(y_group_0, y_new_0);
+				module->connect(y_group_1, y_new_1);
+
+				module->remove(cell);
+				did_something = true;
+				goto next_cell;
+			}
+		}
+
 		if (do_fine)
 		{
 			if (cell->type.in(ID($not), ID($pos), ID($and), ID($or), ID($xor), ID($xnor)))
@@ -905,7 +1047,7 @@ skip_fine_alu:
 			}
 		}
 
-		if (cell->type.in(ID($shiftx), ID($shift))) {
+		if (cell->type.in(ID($shiftx), ID($shift)) && (cell->type == ID($shiftx) || !cell->getParam(ID::A_SIGNED).as_bool())) {
 			SigSpec sig_a = assign_map(cell->getPort(ID::A));
 			int width;
 			bool trim_x = cell->type == ID($shiftx) || !keepdc;
@@ -1152,7 +1294,7 @@ skip_fine_alu:
 			goto next_cell;
 		}
 
-		if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)) && assign_map(cell->getPort(ID::B)).is_fully_const())
+		if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)) && (keepdc ? assign_map(cell->getPort(ID::B)).is_fully_def() : assign_map(cell->getPort(ID::B)).is_fully_const()))
 		{
 			bool sign_ext = cell->type == ID($sshr) && cell->getParam(ID::A_SIGNED).as_bool();
 			int shift_bits = assign_map(cell->getPort(ID::B)).as_int(cell->type.in(ID($shift), ID($shiftx)) && cell->getParam(ID::B_SIGNED).as_bool());
@@ -1163,7 +1305,7 @@ skip_fine_alu:
 			RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
 			RTLIL::SigSpec sig_y(cell->type == ID($shiftx) ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam(ID::Y_WIDTH).as_int());
 
-			if (GetSize(sig_a) < GetSize(sig_y))
+			if (cell->type != ID($shiftx) && GetSize(sig_a) < GetSize(sig_y))
 				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
 
 			for (int i = 0; i < GetSize(sig_y); i++) {
@@ -1446,6 +1588,31 @@ skip_identity:
 				goto next_cell; \
 			} \
 		}
+#define FOLD_2ARG_SIMPLE_CELL(_t, B_ID) \
+		if (cell->type == ID($##_t)) { \
+			RTLIL::SigSpec a = cell->getPort(ID::A); \
+			RTLIL::SigSpec b = cell->getPort(B_ID); \
+			assign_map.apply(a), assign_map.apply(b); \
+			if (a.is_fully_const() && b.is_fully_const()) { \
+				RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const())); \
+				cover("opt.opt_expr.const.$" #_t); \
+				replace_cell(assign_map, module, cell, stringf("%s, %s", log_signal(a), log_signal(b)), ID::Y, y); \
+				goto next_cell; \
+			} \
+		}
+#define FOLD_MUX_CELL(_t) \
+		if (cell->type == ID($##_t)) { \
+			RTLIL::SigSpec a = cell->getPort(ID::A); \
+			RTLIL::SigSpec b = cell->getPort(ID::B); \
+			RTLIL::SigSpec s = cell->getPort(ID::S); \
+			assign_map.apply(a), assign_map.apply(b), assign_map.apply(s); \
+			if (a.is_fully_const() && b.is_fully_const() && s.is_fully_const()) { \
+				RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const(), s.as_const())); \
+				cover("opt.opt_expr.const.$" #_t); \
+				replace_cell(assign_map, module, cell, stringf("%s, %s, %s", log_signal(a), log_signal(b), log_signal(s)), ID::Y, y); \
+				goto next_cell; \
+			} \
+		}
 
 		FOLD_1ARG_CELL(not)
 		FOLD_2ARG_CELL(and)
@@ -1477,6 +1644,9 @@ skip_identity:
 		FOLD_2ARG_CELL(gt)
 		FOLD_2ARG_CELL(ge)
 
+		FOLD_2ARG_CELL(eqx)
+		FOLD_2ARG_CELL(nex)
+
 		FOLD_2ARG_CELL(add)
 		FOLD_2ARG_CELL(sub)
 		FOLD_2ARG_CELL(mul)
@@ -1489,6 +1659,13 @@ skip_identity:
 		FOLD_1ARG_CELL(pos)
 		FOLD_1ARG_CELL(neg)
 
+		FOLD_MUX_CELL(mux);
+		FOLD_MUX_CELL(pmux);
+		FOLD_2ARG_SIMPLE_CELL(bmux, ID::S);
+		FOLD_2ARG_SIMPLE_CELL(demux, ID::S);
+		FOLD_2ARG_SIMPLE_CELL(bweqx, ID::B);
+		FOLD_MUX_CELL(bwmux);
+
 		// be very conservative with optimizing $mux cells as we do not want to break mux trees
 		if (cell->type == ID($mux)) {
 			RTLIL::SigSpec input = assign_map(cell->getPort(ID::S));
diff --git a/passes/sat/formalff.cc b/passes/sat/formalff.cc
index 962e350a1..e36379096 100644
--- a/passes/sat/formalff.cc
+++ b/passes/sat/formalff.cc
@@ -532,12 +532,14 @@ struct FormalFfPass : public Pass {
 						if ((int)bits.size() == ff.val_init.size()) {
 							// This check is only to make the private names more helpful for debugging
 							ff.is_anyinit = true;
+							ff.is_fine = false;
 							emit = true;
 							break;
 						}
 
 						auto slice = ff.slice(bits);
 						slice.is_anyinit = is_anyinit;
+						slice.is_fine = false;
 						slice.emit();
 					}
 				}
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc
index bf33c9ce3..1f64c0216 100644
--- a/passes/sat/miter.cc
+++ b/passes/sat/miter.cc
@@ -30,6 +30,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
 	bool flag_make_outputs = false;
 	bool flag_make_outcmp = false;
 	bool flag_make_assert = false;
+	bool flag_make_cover = false;
 	bool flag_flatten = false;
 	bool flag_cross = false;
 
@@ -54,6 +55,10 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
 			flag_make_assert = true;
 			continue;
 		}
+		if (args[argidx] == "-make_cover") {
+			flag_make_cover = true;
+			continue;
+		}
 		if (args[argidx] == "-flatten") {
 			flag_flatten = true;
 			continue;
@@ -237,6 +242,12 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
 				miter_module->connect(RTLIL::SigSig(w_cmp, this_condition));
 			}
 
+			if (flag_make_cover)
+			{
+				auto cover_condition = miter_module->Not(NEW_ID, this_condition);
+				miter_module->addCover("\\cover_" + RTLIL::unescape_id(gold_wire->name), cover_condition, State::S1);
+			}
+
 			all_conditions.append(this_condition);
 		}
 	}
@@ -402,6 +413,9 @@ struct MiterPass : public Pass {
 		log("    -make_assert\n");
 		log("        also create an 'assert' cell that checks if trigger is always low.\n");
 		log("\n");
+		log("    -make_cover\n");
+		log("        also create a 'cover' cell for each gold/gate output pair.\n");
+		log("\n");
 		log("    -flatten\n");
 		log("        call 'flatten -wb; opt_expr -keepdc -undriven;;' on the miter circuit.\n");
 		log("\n");
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 1cd1ebc71..e8dda4c45 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -509,7 +509,7 @@ struct SimInstance
 		}
 	}
 
-	bool update_ph2()
+	bool update_ph2(bool gclk)
 	{
 		bool did_something = false;
 
@@ -567,7 +567,8 @@ struct SimInstance
 			}
 			if (ff_data.has_gclk) {
 				// $ff
-				current_q = ff.past_d;
+				if (gclk)
+					current_q = ff.past_d;
 			}
 			if (set_state(ff_data.sig_q, current_q))
 				did_something = true;
@@ -616,7 +617,7 @@ struct SimInstance
 		}
 
 		for (auto it : children)
-			if (it.second->update_ph2()) {
+			if (it.second->update_ph2(gclk)) {
 				dirty_children.insert(it.second);
 				did_something = true;
 			}
@@ -985,7 +986,7 @@ struct SimWorker : SimShared
 			writer->write(use_signal);
 	}
 
-	void update()
+	void update(bool gclk)
 	{
 		while (1)
 		{
@@ -997,7 +998,7 @@ struct SimWorker : SimShared
 			if (debug)
 				log("\n-- ph2 --\n");
 
-			if (!top->update_ph2())
+			if (!top->update_ph2(gclk))
 				break;
 		}
 
@@ -1047,7 +1048,7 @@ struct SimWorker : SimShared
 		set_inports(clock, State::Sx);
 		set_inports(clockn, State::Sx);
 
-		update();
+		update(false);
 
 		register_output_step(0);
 
@@ -1060,7 +1061,7 @@ struct SimWorker : SimShared
 			set_inports(clock, State::S0);
 			set_inports(clockn, State::S1);
 
-			update();
+			update(true);
 			register_output_step(10*cycle + 5);
 
 			if (debug)
@@ -1076,7 +1077,7 @@ struct SimWorker : SimShared
 				set_inports(resetn, State::S1);
 			}
 
-			update();
+			update(true);
 			register_output_step(10*cycle + 10);
 		}
 
@@ -1193,7 +1194,7 @@ struct SimWorker : SimShared
 					initial = false;
 				}
 				if (did_something)
-					update();
+					update(true);
 				register_output_step(time);
 
 				bool status = top->checkSignals();
@@ -1342,12 +1343,12 @@ struct SimWorker : SimShared
 						set_inports(clock, State::S0);
 						set_inports(clockn, State::S1);
 					}
-					update();
+					update(true);
 					register_output_step(10*cycle);
 					if (!multiclock && cycle) {
 						set_inports(clock, State::S0);
 						set_inports(clockn, State::S1);
-						update();
+						update(true);
 						register_output_step(10*cycle + 5);
 					}
 					cycle++;
@@ -1419,12 +1420,12 @@ struct SimWorker : SimShared
 						log("Simulating cycle %d.\n", cycle);
 					set_inports(clock, State::S1);
 					set_inports(clockn, State::S0);
-					update();
+					update(true);
 					register_output_step(10*cycle+0);
 					if (!multiclock) {
 						set_inports(clock, State::S0);
 						set_inports(clockn, State::S1);
-						update();
+						update(true);
 						register_output_step(10*cycle+5);
 					}
 					cycle++;
diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc
index 98ccfc303..1b834fabc 100644
--- a/passes/techmap/Makefile.inc
+++ b/passes/techmap/Makefile.inc
@@ -31,6 +31,7 @@ OBJS += passes/techmap/dffinit.o
 OBJS += passes/techmap/pmuxtree.o
 OBJS += passes/techmap/bmuxmap.o
 OBJS += passes/techmap/demuxmap.o
+OBJS += passes/techmap/bwmuxmap.o
 OBJS += passes/techmap/muxcover.o
 OBJS += passes/techmap/aigmap.o
 OBJS += passes/techmap/tribuf.o
diff --git a/passes/techmap/bwmuxmap.cc b/passes/techmap/bwmuxmap.cc
new file mode 100644
index 000000000..7fe1cded7
--- /dev/null
+++ b/passes/techmap/bwmuxmap.cc
@@ -0,0 +1,70 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2022  Jannis Harder <jix@yosyshq.com> <me@jix.one>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct BwmuxmapPass : public Pass {
+	BwmuxmapPass() : Pass("bwmuxmap", "replace $bwmux cells with equivalent logic") {}
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    bwmxumap [options] [selection]\n");
+		log("\n");
+		log("This pass replaces $bwmux cells with equivalent logic\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		log_header(design, "Executing BWMUXMAP pass.\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			// if (args[argidx] == "-arg") {
+			// 	continue;
+			// }
+			break;
+		}
+
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules())
+		for (auto cell : module->selected_cells())
+		{
+			if (cell->type != ID($bwmux))
+				continue;
+			auto &sig_y = cell->getPort(ID::Y);
+			auto &sig_a = cell->getPort(ID::A);
+			auto &sig_b = cell->getPort(ID::B);
+			auto &sig_s = cell->getPort(ID::S);
+
+			auto not_s = module->Not(NEW_ID, sig_s);
+			auto masked_b = module->And(NEW_ID, sig_s, sig_b);
+			auto masked_a = module->And(NEW_ID, not_s, sig_a);
+			module->addOr(NEW_ID, masked_a, masked_b, sig_y);
+
+			module->remove(cell);
+		}
+	}
+} BwmuxmapPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index f75b82919..11692b715 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -58,28 +58,17 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
 	RTLIL::SigSpec sig_b = cell->getPort(ID::B);
 	RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
 
-	sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
-	sig_b.extend_u0(GetSize(sig_y), cell->parameters.at(ID::B_SIGNED).as_bool());
-
-	if (cell->type == ID($xnor))
-	{
-		RTLIL::SigSpec sig_t = module->addWire(NEW_ID, GetSize(sig_y));
-
-		for (int i = 0; i < GetSize(sig_y); i++) {
-			RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
-			gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
-			gate->setPort(ID::A, sig_t[i]);
-			gate->setPort(ID::Y, sig_y[i]);
-		}
-
-		sig_y = sig_t;
+	if (cell->type != ID($bweqx)) {
+		sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
+		sig_b.extend_u0(GetSize(sig_y), cell->parameters.at(ID::B_SIGNED).as_bool());
 	}
 
 	IdString gate_type;
-	if (cell->type == ID($and))  gate_type = ID($_AND_);
-	if (cell->type == ID($or))   gate_type = ID($_OR_);
-	if (cell->type == ID($xor))  gate_type = ID($_XOR_);
-	if (cell->type == ID($xnor)) gate_type = ID($_XOR_);
+	if (cell->type == ID($and))   gate_type = ID($_AND_);
+	if (cell->type == ID($or))    gate_type = ID($_OR_);
+	if (cell->type == ID($xor))   gate_type = ID($_XOR_);
+	if (cell->type == ID($xnor))  gate_type = ID($_XNOR_);
+	if (cell->type == ID($bweqx)) gate_type = ID($_XNOR_);
 	log_assert(!gate_type.empty());
 
 	for (int i = 0; i < GetSize(sig_y); i++) {
@@ -284,6 +273,23 @@ void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
 	}
 }
 
+void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell)
+{
+	RTLIL::SigSpec sig_a = cell->getPort(ID::A);
+	RTLIL::SigSpec sig_b = cell->getPort(ID::B);
+	RTLIL::SigSpec sig_s = cell->getPort(ID::S);
+	RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
+
+	for (int i = 0; i < GetSize(sig_y); i++) {
+		RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
+		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+		gate->setPort(ID::A, sig_a[i]);
+		gate->setPort(ID::B, sig_b[i]);
+		gate->setPort(ID::S, sig_s[i]);
+		gate->setPort(ID::Y, sig_y[i]);
+	}
+}
+
 void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell)
 {
 	RTLIL::SigSpec sig_a = cell->getPort(ID::A);
@@ -409,6 +415,7 @@ void simplemap_get_mappers(dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)>
 	mappers[ID($or)]          = simplemap_bitop;
 	mappers[ID($xor)]         = simplemap_bitop;
 	mappers[ID($xnor)]        = simplemap_bitop;
+	mappers[ID($bweqx)]       = simplemap_bitop;
 	mappers[ID($reduce_and)]  = simplemap_reduce;
 	mappers[ID($reduce_or)]   = simplemap_reduce;
 	mappers[ID($reduce_xor)]  = simplemap_reduce;
@@ -422,6 +429,7 @@ void simplemap_get_mappers(dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)>
 	mappers[ID($ne)]          = simplemap_eqne;
 	mappers[ID($nex)]         = simplemap_eqne;
 	mappers[ID($mux)]         = simplemap_mux;
+	mappers[ID($bwmux)]       = simplemap_bwmux;
 	mappers[ID($tribuf)]      = simplemap_tribuf;
 	mappers[ID($bmux)]        = simplemap_bmux;
 	mappers[ID($lut)]         = simplemap_lut;
diff --git a/passes/techmap/simplemap.h b/passes/techmap/simplemap.h
index c7654f68c..30cc1ccfe 100644
--- a/passes/techmap/simplemap.h
+++ b/passes/techmap/simplemap.h
@@ -31,6 +31,7 @@ extern void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell);
 extern void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell);
 extern void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell);
 extern void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell);
+extern void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell);
 extern void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell);
 extern void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell);
 extern void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell);