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passes
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Author
Age
Files
Lines
*
opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.
whitequark
2018-12-05
1
-17
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+163
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opt_lut: always prefer to eliminate 1-LUTs.
whitequark
2018-12-05
1
-19
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+41
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opt_lut: collect and display statistics.
whitequark
2018-12-05
1
-4
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+33
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opt_lut: refactor to use a worker. NFC.
whitequark
2018-12-05
1
-170
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+177
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opt_lut: new pass, to combine LUTs for tighter packing.
whitequark
2018-12-05
2
-0
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+275
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Fix typo
Clifford Wolf
2018-12-04
1
-1
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+1
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Merge pull request #702 from smunaut/min_ce_use
Clifford Wolf
2018-12-04
1
-1
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+36
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dff2dffe: Add option for unmap to only remove DFFE with low CE signal use
Sylvain Munaut
2018-11-27
1
-1
/
+36
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Merge pull request #676 from rafaeltp/master
Clifford Wolf
2018-12-01
1
-10
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+17
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using [i] to access individual bits of SigSpec and merging bits into a tmp Si...
rafaeltp
2018-10-21
1
-11
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+12
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cleaning up for PR
rafaeltp
2018-10-20
1
-2
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+2
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fixing code style
rafaeltp
2018-10-20
1
-1
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+1
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solves #675
rafaeltp
2018-10-20
1
-11
/
+17
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Add iteration limit to "opt_muxtree"
Clifford Wolf
2018-11-20
1
-1
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+17
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DFFLIBMAP: changed 'missing pin' error into a warning with additional reason/...
Niels Moseley
2018-11-06
1
-1
/
+10
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Allow square brackets in liberty identifiers
Clifford Wolf
2018-11-05
1
-2
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+2
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Liberty file newline handling is more relaxed. More descriptive error message
Niels Moseley
2018-11-03
1
-4
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+7
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Report an error when a liberty file contains pin references that reference no...
Niels Moseley
2018-11-03
1
-0
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+3
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Refactor code to avoid code duplication + added comments
Ruben Undheim
2018-10-20
1
-2
/
+5
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Support for SystemVerilog interfaces as a port in the top level module + test...
Ruben Undheim
2018-10-20
1
-5
/
+36
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Merge pull request #672 from daveshah1/fix_bram
Clifford Wolf
2018-10-19
1
-0
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+1
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memory_bram: Reset make_outreg when growing read ports
David Shah
2018-10-19
1
-0
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+1
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Merge pull request #659 from rubund/sv_interfaces
Clifford Wolf
2018-10-18
1
-7
/
+188
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Documentation improvements etc.
Ruben Undheim
2018-10-13
1
-27
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+38
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Support for 'modports' for System Verilog interfaces
Ruben Undheim
2018-10-12
1
-1
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+13
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Synthesis support for SystemVerilog interfaces
Ruben Undheim
2018-10-12
1
-7
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+165
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stop check_signal_in_fanout from traversing FFs
tklam
2018-10-13
1
-2
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+2
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stop check_signal_in_fanout from traversing FFs
tklam
2018-10-13
1
-1
/
+12
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fix bug: pass by reference
tklam
2018-09-26
1
-1
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+1
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Fix issue #639
TK Lam
2018-09-26
1
-0
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+58
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Merge pull request #625 from aman-goel/master
Clifford Wolf
2018-09-14
1
-1
/
+7
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Minor revision to -expose in setundef pass
Aman Goel
2018-09-10
1
-1
/
+7
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Fixed minor typo in "sim" help message
acw1251
2018-09-12
1
-1
/
+1
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Merge pull request #606 from cr1901/show-win
Clifford Wolf
2018-08-19
1
-3
/
+20
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Update show pass documentation with Windows caveats.
William D. Jones
2018-08-15
1
-1
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+2
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Fix run_command() when using -format and -viewer in show pass.
William D. Jones
2018-08-15
1
-2
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+18
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Revision to expose option in setundef pass
Aman Goel
2018-08-18
1
-154
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+123
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Merge pull request #3 from YosysHQ/master
Aman Goel
2018-08-18
121
-263
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+411
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Merge pull request #591 from hzeller/virtual-override
Clifford Wolf
2018-08-15
120
-265
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+264
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Consistent use of 'override' for virtual methods in derived classes.
Henner Zeller
2018-07-20
120
-265
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+264
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Add missing <deque> include (MSVC build fix)
Clifford Wolf
2018-07-22
1
-0
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+1
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Add async2sync pass
Clifford Wolf
2018-07-19
2
-0
/
+148
*
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Merge pull request #2 from YosysHQ/master
Aman Goel
2018-07-18
3
-3
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+155
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ecp5: Adding synchronous set/reset support
David Shah
2018-07-14
3
-3
/
+155
*
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Merging with official repo
Aman Goel
2018-07-04
8
-65
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+236
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Add automatic verific import in hierarchy command
Clifford Wolf
2018-06-20
1
-1
/
+19
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Be slightly less aggressive in "deminout" pass
Clifford Wolf
2018-06-19
1
-4
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+28
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Include module name for area summary stats
Edmond Cote
2018-06-18
1
-4
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+4
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Add setundef -anyseq / -anyconst support to -undriven mode
Clifford Wolf
2018-06-01
1
-3
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+11
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Add "setundef -anyconst"
Clifford Wolf
2018-06-01
1
-20
/
+41
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