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* Merge pull request #1585 from YosysHQ/eddie/fix_abc9_lutEddie Hung2019-12-201-19/+18
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| * Interpret "abc9 -lut" as lut string only if [0-9:]Eddie Hung2019-12-181-19/+18
* | Merge pull request #1581 from YosysHQ/clifford/fix1565Eddie Hung2019-12-191-1/+1
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| * Fix sim for assignments with lhs<rhs size, fixes #1565Clifford Wolf2019-12-171-1/+1
* | Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2019-12-183-2/+147
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| * \ Merge pull request #1572 from nakengelhardt/scratchpad_passEddie Hung2019-12-182-0/+131
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| | * | use extra_argsN. Engelhardt2019-12-181-1/+1
| | * | add assert option to scratchpad commandN. Engelhardt2019-12-161-5/+44
| | * | add periods and newlines to help messageN. Engelhardt2019-12-131-5/+5
| | * | add test and make help message more verboseN. Engelhardt2019-12-121-1/+6
| | * | add a command to read/modify scratchpad contentsN. Engelhardt2019-12-122-0/+87
| * | | xilinx: Add xilinx_dffopt pass (#1557)Marcin Kościelnicki2019-12-181-2/+16
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* / | CleanupEddie Hung2019-12-171-11/+7
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* | Enforce non-existenceEddie Hung2019-12-161-0/+4
* | Update docEddie Hung2019-12-161-4/+6
* | More sloppiness, thanks @dh73 for spottingEddie Hung2019-12-161-4/+4
* | OopsEddie Hung2019-12-161-4/+1
* | Implement 'attributes' grammarEddie Hung2019-12-161-80/+88
* | Merge branch 'diego/memattr' of https://github.com/dh73/yosys into diego/memattrEddie Hung2019-12-161-1/+90
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| * | Fixing compiler warning/issues. Moving test script to the correct placeDiego H2019-12-161-8/+8
| * | Merging attribute rules into a single match block; Adding testsDiego H2019-12-151-68/+80
| * | Refactoring memory attribute matching based on IEEE 1364.1 and Tool specificDiego H2019-12-131-0/+77
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* / Fix opt_expr.eqneq.cmpzero debug printAlyssa Milburn2019-12-151-1/+1
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* Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attrEddie Hung2019-12-091-8/+67
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| * ice40_wrapcarry -unwrap to preserve 'src' attributeEddie Hung2019-12-091-1/+9
| * -unwrap to create $lut not SB_LUT4 for opt_lutEddie Hung2019-12-091-7/+5
| * Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4Eddie Hung2019-12-091-7/+11
| * ice40_wrapcarry to really preserve attributes via -unwrap optionEddie Hung2019-12-091-17/+55
| * Drop keep=0 attributes on SB_CARRYEddie Hung2019-12-061-0/+8
| * Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPEREddie Hung2019-12-051-0/+1
| * ice40_wrapcarry to preserve SB_CARRY's attributesEddie Hung2019-12-031-0/+2
* | iopadmap: Refactor and fix tristate buffer mapping. (#1527)Marcin Kościelnicki2019-12-041-146/+97
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* abc9: Fix breaking of SCCsDavid Shah2019-12-011-29/+40
* Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladdEddie Hung2019-11-271-3/+3
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| * Check for either sign or zero extension for postAdd packingEddie Hung2019-11-261-3/+3
* | Merge pull request #1501 from YosysHQ/dave/mem_copy_attrClifford Wolf2019-11-271-0/+4
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| * | memory_collect: Copy attr from RTLIL::Memory to cellDavid Shah2019-11-181-0/+4
* | | opt_share: Fix handling of fine cells.Marcin Kościelnicki2019-11-271-4/+11
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* | clkbufmap: Add support for inverters in clock path.Marcin Kościelnicki2019-11-251-0/+41
* | Add "opt_mem" passClifford Wolf2019-11-223-0/+146
* | proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usageDavid Shah2019-11-211-4/+16
* | Fix #1462, #1480.Marcin Kościelnicki2019-11-192-9/+11
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* Fix #1496.Marcin Kościelnicki2019-11-181-4/+8
* Merge pull request #1492 from YosysHQ/dave/wreduce-fix-arstClifford Wolf2019-11-171-4/+10
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| * wreduce: Don't trim zeros or sext when not matching ARST_VALUEDavid Shah2019-11-141-4/+10
* | Merge pull request #1490 from YosysHQ/clifford/autonameClifford Wolf2019-11-142-0/+135
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| * Add "autoname" pass and use it in "synth_ice40"Clifford Wolf2019-11-132-0/+135
* | Merge pull request #1488 from whitequark/flowmap-fixeswhitequark2019-11-131-2/+3
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| * flowmap: when doing mincut, ensure source is always in X, not X̅.whitequark2019-11-121-1/+2
| * flowmap: don't break if that creates a k+2 (and larger) LUT either.whitequark2019-11-111-1/+1
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