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author | Eddie Hung <eddie@fpgeh.com> | 2019-12-16 14:48:53 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-16 14:48:53 -0800 |
commit | 187e1c46e61dc910bf591625f7034b052ba928a7 (patch) | |
tree | 2b8a56d3df011761a1c2b09186085330057bb022 /passes | |
parent | 378d9e6e0c16e13cf161aec283ab366e2462745c (diff) | |
download | yosys-187e1c46e61dc910bf591625f7034b052ba928a7.tar.gz yosys-187e1c46e61dc910bf591625f7034b052ba928a7.tar.bz2 yosys-187e1c46e61dc910bf591625f7034b052ba928a7.zip |
Update doc
Diffstat (limited to 'passes')
-rw-r--r-- | passes/memory/memory_bram.cc | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 29dc4ce07..7f551134a 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -1314,10 +1314,12 @@ struct MemoryBramPass : public Pass { log(" dcells ....... number of cells in 'data-direction'\n"); log(" cells ........ total number of cells (acells*dcells*dups)\n"); log("\n"); - log("A match containing the condition 'attribute' followed by a name and optional\n"); - log("value requires that the memory contains the given attribute name and value\n"); - log("(if specified) or that the attribute is not present (prepending a '!')\n"); - log("or the value is empty (if value is not specified\n)."); + log("A match containing the command 'attribute' followed by a list of space\n"); + log("separated 'name[=string_value]' values requires that the memory contains any\n"); + log("one of the given attribute name and string values (where specified), or name\n"); + log("and integer 1 value (if no string_value given, since Verilog will interpret\n"); + log("'(* attr *)' as '(* attr=1 *)').\n"); + log("A name prefixed with '!' indicates that the attribute must not exist.\n"); log("\n"); log("The interface for the created bram instances is derived from the bram\n"); log("description. Use 'techmap' to convert the created bram instances into\n"); |