| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-27 | 3 | -7/+18 |
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| | * | Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd | Eddie Hung | 2019-11-27 | 1 | -3/+3 |
| | |\ | | | | | | | xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder | ||||
| | | * | Check for either sign or zero extension for postAdd packing | Eddie Hung | 2019-11-26 | 1 | -3/+3 |
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| | * | | Merge pull request #1501 from YosysHQ/dave/mem_copy_attr | Clifford Wolf | 2019-11-27 | 1 | -0/+4 |
| | |\ \ | | | | | | | | | memory_collect: Copy attr from RTLIL::Memory to cell | ||||
| | | * | | memory_collect: Copy attr from RTLIL::Memory to cell | David Shah | 2019-11-18 | 1 | -0/+4 |
| | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | | | opt_share: Fix handling of fine cells. | Marcin Kościelnicki | 2019-11-27 | 1 | -4/+11 |
| | | |/ | |/| | | | | | | | Fixes #1525. | ||||
| * | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-27 | 1 | -7/+3 |
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| | * | | | Do not replace constants with same wire | Eddie Hung | 2019-11-27 | 1 | -7/+3 |
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| * | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-27 | 1 | -47/+71 |
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| | * | | | Cleanup | Eddie Hung | 2019-11-27 | 1 | -5/+3 |
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| | * | | | Check for nullptr | Eddie Hung | 2019-11-27 | 1 | -1/+1 |
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| | * | | | Stray log_dump | Eddie Hung | 2019-11-27 | 1 | -1/+0 |
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| | * | | | Revert "submod to bitty rather bussy, for bussy wires used as input and output" | Eddie Hung | 2019-11-27 | 1 | -40/+71 |
| | | | | | | | | | | | | | | | | | This reverts commit cba3073026711e7683c46ba091c56a5c5a041a45. | ||||
| | * | | | Promote output wires in sigmap so that can be detected | Eddie Hung | 2019-11-26 | 1 | -8/+4 |
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| | * | | | Fix submod -hidden | Eddie Hung | 2019-11-26 | 1 | -5/+6 |
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| | * | | | Add -hidden option to submod | Eddie Hung | 2019-11-26 | 1 | -11/+25 |
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| | * | | | Update docs with bullet points | Eddie Hung | 2019-11-26 | 1 | -10/+9 |
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| | * | | | Move \init from source wire to submod if output port | Eddie Hung | 2019-11-25 | 1 | -0/+7 |
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| * | | | | Fix submod -hidden | Eddie Hung | 2019-11-26 | 1 | -5/+6 |
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| * | | | | clkpart to use 'submod -hidden' | Eddie Hung | 2019-11-26 | 1 | -1/+1 |
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| * | | | | Add -hidden option to submod | Eddie Hung | 2019-11-26 | 1 | -20/+40 |
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| * | | | | Fix debug | Eddie Hung | 2019-11-25 | 1 | -3/+3 |
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| * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-25 | 1 | -0/+41 |
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| | * | | | clkbufmap: Add support for inverters in clock path. | Marcin Kościelnicki | 2019-11-25 | 1 | -0/+41 |
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| * | | | | abc9 to contain time call | Eddie Hung | 2019-11-25 | 1 | -1/+1 |
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| * | | | | abc9 to no longer to clock partitioning, operate on whole modules only | Eddie Hung | 2019-11-25 | 1 | -139/+32 |
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| * | | | | clkpart to analyse async flops too | Eddie Hung | 2019-11-25 | 1 | -0/+8 |
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| * | | | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-23 | 1 | -2/+3 |
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| | * | | | | More oopsies | Eddie Hung | 2019-11-23 | 1 | -2/+3 |
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| * | | | | | Conditioning abc9 on POs not accurate due to cells | Eddie Hung | 2019-11-23 | 1 | -15/+6 |
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| * | | | | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-23 | 1 | -13/+27 |
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| | * | | | | Print ".en=" only if there is an enable signal | Eddie Hung | 2019-11-23 | 1 | -1/+1 |
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| | * | | | | Escape IdStrings | Eddie Hung | 2019-11-23 | 1 | -3/+2 |
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| | * | | | | More sane naming of submod | Eddie Hung | 2019-11-23 | 1 | -2/+2 |
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| | * | | | | Add -set_attr option, -unpart to take attr name | Eddie Hung | 2019-11-23 | 1 | -10/+25 |
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| * | | | | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-23 | 1 | -18/+34 |
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| | * | | | | Do not use log_signal() for empty SigSpec to prevent "{ }" | Eddie Hung | 2019-11-22 | 1 | -2/+4 |
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| | * | | | | Call submod once, more meaningful submod names, ignore largest domain | Eddie Hung | 2019-11-22 | 1 | -18/+32 |
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| * | | | | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-22 | 3 | -1/+1 |
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| | * | | | | Move clkpart into passes/hierarchy | Eddie Hung | 2019-11-22 | 3 | -1/+1 |
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| * | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -48/+39 |
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| | * | | | | submod to bitty rather bussy, for bussy wires used as input and output | Eddie Hung | 2019-11-22 | 1 | -48/+39 |
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| * | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -2/+10 |
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| | * | | | | Constant driven signals are also an input to submodules | Eddie Hung | 2019-11-22 | 1 | -2/+10 |
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| * | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -1/+0 |
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| | * | | | | Oops | Eddie Hung | 2019-11-22 | 1 | -1/+0 |
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| * | | | | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -8/+9 |
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| | * | | | | Only action if there is more than one clock domain | Eddie Hung | 2019-11-22 | 1 | -7/+8 |
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| | * | | | | Replace TODO | Eddie Hung | 2019-11-22 | 1 | -1/+1 |
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| * | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -1/+19 |
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index : iCE40/yosys | |
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