iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27	3	-7/+11
*	Added sat -set-def/-set-*-undef support	Clifford Wolf	2013-12-27	1	-5/+66
*	Renamed sat -set-undef to -set-any-undef	Clifford Wolf	2013-12-27	1	-20/+20
*	Fixed dfflibmap for unused output ports	Clifford Wolf	2013-12-21	1	-0/+1
*	Now prefer smallest cells in dfflibmap	Clifford Wolf	2013-12-21	1	-2/+22
*	Cleanup of dfflibmap cellmap exploration code	Clifford Wolf	2013-12-20	1	-17/+20
*	Further improved dfflibmap cellmap exploration	Clifford Wolf	2013-12-20	1	-14/+18
*	Fixed dfflibmap endless-loop bug	Clifford Wolf	2013-12-20	1	-0/+1
*	Prefer non-inverted clocks in dfflibmap	Clifford Wolf	2013-12-19	1	-6/+8
*	Added sat -max_undef feature	Clifford Wolf	2013-12-07	1	-11/+50
*	Added "sat" undef support and "sat -set-init" options	Clifford Wolf	2013-12-07	1	-40/+146
*	Fixed compiler warining in passes/sat/eval.cc	Clifford Wolf	2013-12-07	1	-2/+2
*	Added eval -set-undef and eval -table	Clifford Wolf	2013-12-07	1	-11/+140
*	Fixes in fsm detect/extract for better detection of non-fsm circuits	Clifford Wolf	2013-12-06	2	-4/+4
*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04	2	-2/+2
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	12	-34/+24
*	Fixed submod for non-primitive cells	Clifford Wolf	2013-12-02	1	-0/+1
*	Fixed submod for non-cleaned designs	Clifford Wolf	2013-12-02	1	-1/+4
*	A fix in memory_dff for write ports with static addresses	Clifford Wolf	2013-12-01	1	-10/+10
*	Progress on AppNote 011	Clifford Wolf	2013-11-29	1	-0/+4
*	Added pattern support to "ls" command	Clifford Wolf	2013-11-28	1	-30/+35
*	Improved ID matching scheme in select (and thus for all commands)	Clifford Wolf	2013-11-28	1	-2/+12
*	Fixes and improvements in "show" command	Clifford Wolf	2013-11-28	1	-10/+42
*	Added "src" attribute to processes	Clifford Wolf	2013-11-28	1	-1/+4
*	Added support for "show -pause" and "show -format dot"	Clifford Wolf	2013-11-28	1	-6/+30
*	Tighter integration of ABC build	Clifford Wolf	2013-11-27	1	-0/+2
*	Started implementing undef support in "sat" command	Clifford Wolf	2013-11-25	1	-12/+103
*	Bugfixes in new "stat" command	Clifford Wolf	2013-11-25	1	-7/+1
*	Added "stat" command	Clifford Wolf	2013-11-25	2	-0/+219
*	Improvements in satgen undef handling	Clifford Wolf	2013-11-25	1	-14/+39
*	Improvements in satgen undef handling	Clifford Wolf	2013-11-25	1	-4/+20
*	Started implementing undef handling in satgen	Clifford Wolf	2013-11-25	1	-9/+30
*	Using simplemap mappers from techmap	Clifford Wolf	2013-11-24	2	-28/+64
*	Added simplemap pass	Clifford Wolf	2013-11-24	2	-0/+518
*	Added module->avail_parameters (for advanced techmap features)	Clifford Wolf	2013-11-24	1	-2/+8
*	Added techmap -D and -I options	Clifford Wolf	2013-11-24	1	-2/+16
*	Added "techmap -share_map" option	Clifford Wolf	2013-11-24	1	-0/+9
*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24	1	-60/+0
*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24	2	-2/+2
*	Fixed "flatten" top-module detection: Only use on fully selected designs	Clifford Wolf	2013-11-24	1	-3/+4
*	Added "top" attribute to mark top module in hierarchy	Clifford Wolf	2013-11-24	2	-3/+43
*	Improved handling of techmap special wires	Clifford Wolf	2013-11-23	1	-1/+3
*	Added more generic _TECHMAP_ wire mechanism to techmap pass	Clifford Wolf	2013-11-23	1	-77/+185
*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22	4	-9/+9
*	Updated abc	Clifford Wolf	2013-11-21	1	-10/+27
*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21	3	-0/+117
*	Fixed a bug in "add -global_input"	Clifford Wolf	2013-11-21	1	-16/+17
*	Added "proc_arst -global_arst" feature	Clifford Wolf	2013-11-20	2	-8/+81
*	Added "add" command (only wires for now)	Clifford Wolf	2013-11-20	2	-0/+155
*	Renamed temp module generated by "abc" pass from "logic" to "netlist"	Clifford Wolf	2013-11-19	2	-6/+6