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| author | Clifford Wolf <clifford@clifford.at> | 2013-12-04 14:24:44 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-12-04 14:24:44 +0100 |
| commit | f4b46ed31e5f5c41bbd4ee1fdf996ecdc2010174 (patch) | |
| tree | ab513e840494e2be4b04149a149f7c12e605e7e4 /passes | |
| parent | 93a70959f3f67ffcee8159b18a5f68904e32a074 (diff) | |
| download | yosys-f4b46ed31e5f5c41bbd4ee1fdf996ecdc2010174.tar.gz yosys-f4b46ed31e5f5c41bbd4ee1fdf996ecdc2010174.tar.bz2 yosys-f4b46ed31e5f5c41bbd4ee1fdf996ecdc2010174.zip | |
Replaced signed_parameters API with CONST_FLAG_SIGNED
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 2 | ||||
| -rw-r--r-- | passes/techmap/techmap.cc | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 18f058973..d46757029 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -150,7 +150,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla if (design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) continue; RTLIL::Module *mod = design->modules[cell->type]; - cell->type = mod->derive(design, cell->parameters, cell->signed_parameters); + cell->type = mod->derive(design, cell->parameters); cell->parameters.clear(); did_something = true; } diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 8dd96b837..08e314081 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -259,7 +259,7 @@ static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL:: tpl = techmap_cache[key]; } else { if (cell->parameters.size() != 0) { - derived_name = tpl->derive(map, parameters, cell->signed_parameters); + derived_name = tpl->derive(map, parameters); tpl = map->modules[derived_name]; log_continue = true; } |