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* flatten: clarify confusing error message.whitequark2021-01-261-1/+1
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* Merge pull request #2549 from pgadfort/support-multiple-libswhitequark2021-01-251-15/+21
|\ | | | | adding support for passing multiple liberty files to abc
| * adding support for passing multiple liberty files to abcPeter Gadfort2021-01-181-15/+21
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* | Merge pull request #2536 from TobiasFaller/masterMiodrag Milanović2021-01-201-0/+1
|\ \ | |/ |/| Fixed missing goto statement in passes/techmap/abc.cc
| * Fixed missing goto statement in passes/techmap/abc.ccTobias Faller2021-01-121-0/+1
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* | opt_share: Fix X and CO signal width for shifted $alu in opt_share.Marcelina Kościelnicka2021-01-141-2/+2
|/ | | | | | These need to be the same length as actual Y, not visible part of Y. Fixes #2538.
* plugin: enhance no-plugin errorumarcor2020-12-291-1/+5
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* passes/pmgen/pmgen.py: trivial change to remove C++ compiler warningsLarry Doolittle2020-12-231-2/+2
| | | | Verified that the result still builds and passes self-tests
* Fix use-after-free in LUT opt passStefanBruens2020-12-221-2/+4
| | | | | RTLIL::Module::remove(Cell* cell) calls `delete cell`. Any subsequent accesses of `cell` then causes undefined behavior.
* Sign extend port connections where necessaryZachary Snow2020-12-182-3/+10
| | | | | | | | | | | - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265
* Return nice error in pmgen generated code, fixes #2482Miodrag Milanovic2020-12-091-2/+6
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* bugpoint: add -wires option.whitequark2020-12-071-3/+38
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* bugpoint: try to remove whole processes first.whitequark2020-12-071-4/+40
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* bugpoint: accept quoted strings in -grep.whitequark2020-12-071-1/+4
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* bugpoint: add -command option.whitequark2020-12-071-13/+21
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* Add #include needed to build with gcc-11Gabriel Somlo2020-11-261-0/+1
| | | | Suggested by Jeff Law <law@redhat.com>
* Merge pull request #2450 from nitz/sim-vcd-filenamewhitequark2020-11-251-1/+3
|\ | | | | Add rewrite_filename for sim -vcd argument.
| * Add rewrite_filename for sim -vcd argument.Chris Dailey2020-11-241-1/+3
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* | Merge pull request #2428 from whitequark/check-processeswhitequark2020-11-241-22/+55
|\ \ | |/ |/| check: add support for processes
| * check: add support for processes.whitequark2020-11-031-3/+38
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| * check: reformat log/help text to match most other passeswhitequark2020-11-031-19/+17
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* | Expose abc and data paths as globalsMiodrag Milanovic2020-11-062-29/+2
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* This patch adds support for defining the ABC location at runtime instead of ↵Ethan Mahintorabi2020-10-281-1/+6
| | | | | | at compile time. This is helpful in build systems like bazel which do not have stable locations for binaries or directories during the compilation phase. This change should be backwards compatible with the existing behavior.
* Merge pull request #2403 from nakengelhardt/sim_timescaleN. Engelhardt2020-10-221-0/+21
|\ | | | | sim -vcd: add date, version, and option for timescale
| * use strftime instead of put_time for gcc 4.8 compatibilityN. Engelhardt2020-10-211-4/+5
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| * wild guessing at the problem because it builds fine on my machinesN. Engelhardt2020-10-161-0/+3
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| * sim -vcd: add date, version, and option for timescaleN. Engelhardt2020-10-161-0/+17
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* | memory_dff: Fix needlessly duplicating enable bits.Marcelina Kościelnicka2020-10-221-0/+8
| | | | | | | | | | | | | | | | | | When the register being merged into the EN signal happens to be a $sdff, the current code creates a new $mux for every bit, even if they happen to be identical (as is usually the case), preventing proper grouping further down the flow. Fix this by adding a simple cache. Fixes #2409.
* | sim: Use Mem helper.Marcelina Kościelnicka2020-10-211-103/+90
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* | clk2fflogic: Use Mem helper.Marcelina Kościelnicka2020-10-211-68/+45
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* | opt_mem: Use Mem helpers.Marcelina Kościelnicka2020-10-211-81/+6
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* | memory_bram: Use Mem helpers.Marcelina Kościelnicka2020-10-211-121/+90
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* | memory_map: Use Mem helpers.Marcelina Kościelnicka2020-10-211-138/+81
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* | memory_unpack: Use Mem helpers.Marcelina Kościelnicka2020-10-211-106/+10
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* | memory_collect: Use Mem helpers.Marcelina Kościelnicka2020-10-211-223/+9
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* | memory_nordff: Use Mem helpers.Marcelina Kościelnicka2020-10-211-63/+9
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* opt_clean: Better memory handling.Marcelina Kościelnicka2020-10-081-8/+45
| | | | | | | | Previously, `$memwr` and `$meminit` cells were always preserved (along with the memory itself). With this change, they are instead part of the main cell mark-and-sweep pass: a memory (and its `$meminit` and `$memwr` cells) is only preserved iff any associated `$memrd` cell needs to be preserved.
* Validate parameters only when they are usedMiodrag Milanovic2020-09-251-5/+7
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* use the new isPublic() in a few placesN. Engelhardt2020-09-149-17/+17
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* Merge pull request #2356 from whitequark/flatten-techmap-no-tpl_driven-sigmapwhitequark2020-08-272-9/+6
|\ | | | | flatten, techmap: don't canonicalize tpl driven bits via sigmap
| * flatten, techmap: don't canonicalize tpl driven bits via sigmap.whitequark2020-08-262-9/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For connection `assign a = b;`, `sigmap(a)` returns `b`. This is exactly the opposite of the desired canonicalization for driven bits. Consider the following code: module foo(inout a, b); assign a = b; endmodule module bar(output c); foo f(c, 1'b0); endmodule Before this commit, the inout ports would be swapped after flattening (and cause a crash while attempting to drive a constant value). This issue was introduced in 9f772eb9. Fixes #2183.
* | Merge pull request #2358 from whitequark/rename-ilang-to-rtlilwhitequark2020-08-277-24/+24
|\ \ | | | | | | Replace "ILANG" with "RTLIL" everywhere
| * | Replace "ILANG" with "RTLIL" everywhere.whitequark2020-08-267-24/+24
| |/ | | | | | | | | | | | | | | | | | | The only difference between "RTLIL" and "ILANG" is that the latter is the text representation of the former, as opposed to the in-memory graph representation. This distinction serves no purpose but confuses people: it is not obvious that the ILANG backend writes RTLIL graphs. Passes `write_ilang` and `read_ilang` are provided as aliases to `write_rtlil` and `read_rtlil` for compatibility.
* / dfflegalize: Fix decision tree for adffe.Marcelina Kościelnicka2020-08-271-1/+5
|/ | | | | | | | When an adffe is being legalized, and is not natively supported, prioritize unmapping to adff over converting to dffsre if dffsre is not natively supported itself. Fixes #2361.
* proc: Add -nomux switchPeder Bergebakken Sundt2020-08-201-1/+10
| | | | running proc -nomux will ommit the proc_mux pass
* Merge pull request #2344 from YosysHQ/mwk/opt_share-fixesclairexen2020-08-201-223/+138
|\ | | | | opt_share: Refactor, fix some bugs.
| * opt_share: Refactor, fix some bugs.Marcelina Kościelnicka2020-08-171-223/+138
| | | | | | | | | | | | Fixes #2334. Fixes #2335. Fixes #2336.
* | Merge pull request #2337 from YosysHQ/mwk/clean-keep-wireclairexen2020-08-201-4/+9
|\ \ | | | | | | opt_clean: Fix module keep rules.
| * | opt_clean: Fix module keep rules.Marcelina Kościelnicka2020-08-091-4/+9
| |/ | | | | | | | | | | - wires with keep attribute now force a module to be kept - presence of $memwr and $meminit cells no longer forces a module to be kept
* | Merge pull request #2333 from YosysHQ/mwk/peepopt-shiftmul-signedclairexen2020-08-201-5/+1
|\ \ | | | | | | peeopt.shiftmul: Add a signedness check.
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