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| author | Zachary Snow <zach@zachjs.com> | 2020-12-18 12:59:08 -0700 |
|---|---|---|
| committer | Zachary Snow <zach@zachjs.com> | 2020-12-18 20:33:14 -0700 |
| commit | 0d8e5d965f2585e6ed151a9e92d83ee63df6172a (patch) | |
| tree | f2da85bd5aaf90406d3536b64749837d44003eab /passes | |
| parent | 40e35993af6ecb6207f15cc176455ff8d66bcc69 (diff) | |
| download | yosys-0d8e5d965f2585e6ed151a9e92d83ee63df6172a.tar.gz yosys-0d8e5d965f2585e6ed151a9e92d83ee63df6172a.tar.bz2 yosys-0d8e5d965f2585e6ed151a9e92d83ee63df6172a.zip | |
Sign extend port connections where necessary
- Signed cell outputs are sign extended when bound to larger wires
- Signed connections are sign extended when bound to larger cell inputs
- Sign extension is performed in hierarchy and flatten phases
- genrtlil indirects signed constants through signed wires
- Other phases producing RTLIL may need to be updated to preserve
signedness information
- Resolves #1418
- Resolves #2265
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 8 | ||||
| -rw-r--r-- | passes/techmap/flatten.cc | 5 |
2 files changed, 10 insertions, 3 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 225e1feae..3372687e1 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -1233,14 +1233,18 @@ struct HierarchyPass : public Pass { { int n = GetSize(conn.second) - GetSize(w); if (!w->port_input && w->port_output) - module->connect(sig.extract(GetSize(w), n), Const(0, n)); + { + RTLIL::SigSpec out = sig.extract(0, GetSize(w)); + out.extend_u0(GetSize(sig), w->is_signed); + module->connect(sig.extract(GetSize(w), n), out.extract(GetSize(w), n)); + } sig.remove(GetSize(w), n); } else { int n = GetSize(w) - GetSize(conn.second); if (w->port_input && !w->port_output) - sig.append(Const(0, n)); + sig.extend_u0(GetSize(w), sig.is_wire() && sig.as_wire()->is_signed); else sig.append(module->addWire(NEW_ID, n)); } diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index 08978f446..ec5f83fb0 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -180,12 +180,15 @@ struct FlattenWorker RTLIL::Wire *tpl_wire = tpl->wire(port_name); RTLIL::SigSig new_conn; + bool is_signed = false; if (tpl_wire->port_output && !tpl_wire->port_input) { new_conn.first = port_it.second; new_conn.second = tpl_wire; + is_signed = tpl_wire->is_signed; } else if (!tpl_wire->port_output && tpl_wire->port_input) { new_conn.first = tpl_wire; new_conn.second = port_it.second; + is_signed = new_conn.second.is_wire() && new_conn.second.as_wire()->is_signed; } else { SigSpec sig_tpl = tpl_wire, sig_mod = port_it.second; for (int i = 0; i < GetSize(sig_tpl) && i < GetSize(sig_mod); i++) { @@ -204,7 +207,7 @@ struct FlattenWorker if (new_conn.second.size() > new_conn.first.size()) new_conn.second.remove(new_conn.first.size(), new_conn.second.size() - new_conn.first.size()); if (new_conn.second.size() < new_conn.first.size()) - new_conn.second.append(RTLIL::SigSpec(RTLIL::State::S0, new_conn.first.size() - new_conn.second.size())); + new_conn.second.extend_u0(new_conn.first.size(), is_signed); log_assert(new_conn.first.size() == new_conn.second.size()); if (sigmap(new_conn.first).has_const()) |