iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	kernel: big fat patch to use more ID::, otherwise ID()	Eddie Hung	2020-04-02	1	-97/+97
*	kernel: use more ID::*	Eddie Hung	2020-04-02	1	-38/+38
*	More use of IdString::in()	Eddie Hung	2019-08-15	1	-2/+2
*	substr() -> compare()	Eddie Hung	2019-08-07	1	-1/+1
*	RTLIL::S{0,1} -> State::S{0,1}	Eddie Hung	2019-08-07	1	-17/+17
*	stoi -> atoi	Eddie Hung	2019-08-07	1	-2/+2
*	Use std::stoi instead of atoi(<str>.c_str())	Eddie Hung	2019-08-06	1	-2/+2
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
*	Add $live and $fair cell types, add support for s_eventually keyword	Clifford Wolf	2017-02-25	1	-2/+0
*	Removed $predict again	Clifford Wolf	2016-08-28	1	-1/+0
*	Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()	Clifford Wolf	2016-07-25	1	-1/+1
*	Improvements in CellEdgesDatabase	Clifford Wolf	2016-07-24	1	-3/+33
*	Added CellEdgesDatabase API	Clifford Wolf	2016-07-24	1	-0/+96
*	After reading the SV spec, using non-standard predict() instead of expect()	Clifford Wolf	2016-07-21	1	-1/+1
*	Added basic support for $expect cells	Clifford Wolf	2016-07-13	1	-0/+2
*	Improved support for $sop cells	Clifford Wolf	2016-06-17	1	-2/+38
*	Import more std:: stuff into Yosys namespace	Clifford Wolf	2015-10-25	1	-1/+1
*	Added "test_cell -noeval"	Clifford Wolf	2015-09-25	1	-1/+10
*	Re-created command-reference-manual.tex, copied some doc fixes to online help	Clifford Wolf	2015-08-14	1	-1/+1
*	Renamed "aig" to "aigmap"	Clifford Wolf	2015-06-10	1	-4/+4
*	Fixed cellaigs port extending	Clifford Wolf	2015-06-10	1	-0/+7
*	Replaced ezDefaultSAT with ezSatPtr	Clifford Wolf	2015-02-21	1	-5/+5
*	Added "test_cell -muxdiv"	Clifford Wolf	2014-12-25	1	-2/+18
*	Added "test_cell -w" feature	Clifford Wolf	2014-12-25	1	-18/+39
*	Fixed typo in test_cell	Clifford Wolf	2014-10-18	1	-1/+1
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	1	-36/+36
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-0/+4
*	Added $lcu cell type	Clifford Wolf	2014-09-08	1	-1/+26
*	Added "$fa" cell type	Clifford Wolf	2014-09-08	1	-0/+31
*	Added "test_cell -const"	Clifford Wolf	2014-09-08	1	-2/+45
*	Added "test_cell -nosat"	Clifford Wolf	2014-09-07	1	-59/+73
*	Various bug fixes (related to $macc model testing)	Clifford Wolf	2014-09-06	1	-1/+1
*	Added $macc SAT model	Clifford Wolf	2014-09-06	1	-5/+6
*	Added $macc cell type	Clifford Wolf	2014-09-06	1	-2/+53
*	Added "test_cell -script"	Clifford Wolf	2014-09-06	1	-1/+8
*	Removed $bu0 cell type	Clifford Wolf	2014-09-04	1	-1/+0
*	Fixed "test_cells -vlog"	Clifford Wolf	2014-09-03	1	-4/+6
*	Improvements in "test_cell -vlog"	Clifford Wolf	2014-09-02	1	-3/+8
*	Added test_cell -vlog	Clifford Wolf	2014-09-02	1	-2/+79
*	Added SAT testing to test_cell eval stage	Clifford Wolf	2014-09-02	1	-1/+89
*	Added $alu support to test_cell	Clifford Wolf	2014-09-01	1	-1/+22
*	Added "test_cell -simlib -v"	Clifford Wolf	2014-09-01	1	-8/+29
*	Added eval testing to test_cell	Clifford Wolf	2014-08-31	1	-0/+88
*	Added $lut support in test_cell, techmap, satgen	Clifford Wolf	2014-08-31	1	-5/+28
*	Added "test_cell -s <seed>"	Clifford Wolf	2014-08-16	1	-5/+17
*	RIP $safe_pmux	Clifford Wolf	2014-08-14	1	-1/+0
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-3/+3
*	Added "techmap -assert"	Clifford Wolf	2014-07-31	1	-1/+1
*	Improvements in test_cell	Clifford Wolf	2014-07-30	1	-35/+89
*	Added "test_cell" command	Clifford Wolf	2014-07-29	1	-0/+184