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author | Clifford Wolf <clifford@clifford.at> | 2014-07-31 02:21:41 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-31 02:21:41 +0200 |
commit | 6ca0c569d92883b6eac1725204de90aee4af31bc (patch) | |
tree | 46e6171dfa53f66ab5d700bf7ed0a75b96997c8c /passes/tests/test_cell.cc | |
parent | 41555cde1026ecc269071ede4f99d86ff61f7078 (diff) | |
download | yosys-6ca0c569d92883b6eac1725204de90aee4af31bc.tar.gz yosys-6ca0c569d92883b6eac1725204de90aee4af31bc.tar.bz2 yosys-6ca0c569d92883b6eac1725204de90aee4af31bc.zip |
Added "techmap -assert"
Diffstat (limited to 'passes/tests/test_cell.cc')
-rw-r--r-- | passes/tests/test_cell.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index d504cea94..4034f120e 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -104,7 +104,7 @@ struct TestCellPass : public Pass { virtual void execute(std::vector<std::string> args, RTLIL::Design*) { int num_iter = 100; - std::string techmap_cmd = "techmap"; + std::string techmap_cmd = "techmap -assert"; std::string ilang_file; int argidx; |