| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Added "test_cell -simlib -v" | Clifford Wolf | 2014-09-01 | 1 | -8/+29 |
| * | Added eval testing to test_cell | Clifford Wolf | 2014-08-31 | 1 | -0/+88 |
| * | Added $lut support in test_cell, techmap, satgen | Clifford Wolf | 2014-08-31 | 1 | -5/+28 |
| * | Added "test_cell -s <seed>" | Clifford Wolf | 2014-08-16 | 1 | -5/+17 |
| * | RIP $safe_pmux | Clifford Wolf | 2014-08-14 | 1 | -1/+0 |
| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -3/+3 |
| * | Added "techmap -assert" | Clifford Wolf | 2014-07-31 | 1 | -1/+1 |
| * | Improvements in test_cell | Clifford Wolf | 2014-07-30 | 1 | -35/+89 |
| * | Added "test_cell" command | Clifford Wolf | 2014-07-29 | 1 | -0/+184 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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